R5F2123CJFP资料

R8C/22 Group, R8C/23 Group

RENESAS MCU

REJ03B0097-0110

Rev.1.10Mar 16, 2007

1.Overview

This MCU is built using the high-performance silicon gate CMOS process using the R8C/Tiny Series CPU core and ispackaged in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high levelof instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. ThisMCU is equipped with one CAN module and suited to in-vehicle or FA networking.Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/23 Group.

The difference between R8C/22 and R8C/23 Groups is only the existence of the data flash. Their peripheral functionsare the same.

1.1Applications

Automotive, etc.

Rev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

1. Overview

1.2Performance Overview

Table 1.1 outlines the Functions and Specifications for R8C/22 Group and Table 1.2 outlines the Functions andSpecifications for R8C/23 Group.Table 1.1

Functions and Specifications for R8C/22 Group

ItemSpecificationCPUNumber of fundamental instructions89 instructionsMinimum instruction execution time50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)

Operating modeSingle-chipAddress space1 MbyteMemory capacityRefer to Table 1.3 Product Information of R8C/22 GroupPeripheral PortsI/O ports: 41 pins, Input port: 3 pinsFunction TimersTimer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel

(Each timer equipped with 8-bit prescaler)

Timer RD: 16 bits x 2 channel(Circuits of input capture and output compare)Timer RE: With compare match function

Serial interface1 channel (UART0)Clock synchronous I/O, UART1 channel (UART1)UART

Clock synchronous serial interface1 channelI2C bus interface(2), Clock synchronous serial I/O with chip select

LIN moduleHardware LIN: 1 channel(timer RA, UART0)

CAN module1 channel with 2.0B specification: 16 slotsA/D converter 10-bit A/D converter: 1 circuit, 12 channelsWatchdog timer15 bits x 1 channel (with prescaler)Reset start selectable

InterruptInternal: 14 sources, External: 6 sources, Software: 4 sources, Priority level: 7 levels

Clock generation circuits2 circuits XIN clock generation circuit (with on-chip feedback resistor)On-chip oscillator (high speed, low speed)

High-speed on-chip oscillator has frequency adjustmentfunction.

Oscillation stop detection Stop detection of XIN clock oscillationfunction

Voltage detection circuitOn-chipPower-on reset circuit includeOn-chip

Electric Supply voltageVCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(D, J version)CharacteristicsVCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)

VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)

Current consumptionTyp. 12.5 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-chip oscillator stopping)

Typ. 6.0 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping)

Flash Memory Programming and erasure voltageVCC = 2.7 to 5.5 VProgramming and erasure endurance100 timesOperating Ambient Temperature-40 to 85°C-40 to 125°C (option(1))

Package48-pin mold-plastic LQFPNOTES:

1.When using options, be sure to inquire about the specification.

2.I2C bus is a registered trademark of Koninklijke Philips Electronics N.V.

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R8C/22 Group, R8C/23 Group

1. Overview

Table 1.2Functions and Specifications for R8C/23 Group

ItemSpecificationCPUNumber of fundamental instructions89 instructionsMinimum instruction execution time50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)

Operating modeSingle-chipAddress space1 MbyteMemory capacityRefer to Table 1.4 Product Information of R8C/23 GroupPeripheral PortsI/O ports: 41 pins, Input port: 3 pinsFunction TimersTimer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel

(Each timer equipped with 8-bit prescaler)

Timer RD: 16 bits x 2 channel(Circuits of input capture and output compare)Timer RE: With compare match function

Serial interface1 channel (UART0)Clock synchronous I/O, UART1 channel (UART1)UART

Clock synchronous serial interface1 channelI2C bus interface(2), Clock synchronous serial I/O with chip select

LIN moduleHardware LIN: 1 channel(Timer RA, UART0)

CAN module1 channel with 2.0B specification: 16 slotsA/D converter 10-bit A/D converter: 1 circuit, 12 channelsWatchdog timer15 bits x 1 channel (with prescaler)Reset start selectable

InterruptsInternal: 14 sources, External: 6 sources, Software: 4 sources, Priority level: 7 levels

Clock generation circuits2 circuits XIN clock generation circuit (with on-chip feedback resistor)On-chip oscillator (high speed, low speed)

High-speed on-chip oscillator has frequency adjustmentfunction.

Oscillation stop detection Stop detection of XIN clock oscillationfunction

Voltage detection circuitOn-chipPower-on reset circuit includeOn-chip

Electric Supply voltageVCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(D, J version)CharacteristicsVCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)

VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)

Current consumptionTyp. 12.5 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-chip oscillator stopping)

Typ. 6.0 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping)

Flash Memory Programming and erasure voltageVCC = 2.7 to 5.5 VProgramming and erasure endurance10,000 times (data flash)1,000 times (program ROM)Operating Ambient Temperature-40 to 85°C-40 to 125°C (option(1))

Package48-pin mold-plastic LQFPNOTES:

1.When using options, be sure to inquire about the specification.

2.I2C bus is a registered trademark of Koninklijke Philips Electronics N.V.

Rev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

1. Overview

1.3Block Diagram

Figure 1.1 shows a Block Diagram.

8886338I/O portPort P0Port P1Port P2Port P3Port P4Port P6TimerA/D converter(10 bits × 12 channels)UART orclock synchronous serial I/O(8 bits × 1 channel)System clockgeneration circuitXIN-XOUTHigh-speed on-chip oscillatorLow-speed on-chip oscillatorTimer RA (8 bits)Timer RB (8 bits)Timer RD (16 bits × 2 channels)Timer RE (8 bits)UART(8 bits × 1 channel)I2C bus interface orclock synchronous serial I/Owith chip select(8 bits × 1 channel)CAN module(1 channel)LIN module(1 channel)Watchdog timer(15 bits)R8C/Tiny Series CPU coreR0HR1HR2R3A0A1FBR0LR1LSBUSPISPINTBPCFLGMemoryROM(1)RAM(2)MultiplierNOTES:1. ROM size depends on MCU type.2. RAM size depends on MCU type.Figure 1.1Block DiagramRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

1. Overview

1.4Product Information

Product Information for R8C/22 Group

ROM Capacity32 Kbytes48 Kbytes64 Kbytes32 Kbytes48 Kbytes64 Kbytes96 Kbytes128 Kbytes(1)32 Kbytes48 Kbytes64 Kbytes96 Kbytes128 Kbytes(1)

RAM Capacity2 Kbytes2.5 Kbytes3 Kbytes2 Kbytes2.5 Kbytes3 Kbytes5 Kbytes6 Kbytes2 Kbytes2.5 Kbytes3 Kbytes5 Kbytes6 Kbytes

Package TypePLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-A

Current of Mar. 2007Remarks

D versionFlash memory

versionJ version

Table 1.3 lists Product Information of R8C/22 Group and Table 1.4 lists Product Information of R8C/23 Group.Table 1.3

Type No.R5F21226DFP (D)R5F21227DFP (D)R5F21228DFP (D)R5F21226JFPR5F21227JFPR5F21228JFPR5F2122AJFP (D)R5F2122CJFP (D)R5F21226KFPR5F21227KFPR5F21228KFP (D)R5F2122AKFP (D)R5F2122CKFP (D)

K version

NOTE:

1.Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 24. Notes on Emulator Debugger.(D): Under development

Part numberR 5 F 21 22 6 J FPPackage type:FP: PLQP0048KB-A(0.5 mm pin-pitch, 7 mm square body)ClassificationD: Operating ambient temperature -40°C to 85°C (D version)J: Operating ambient temperature -40°C to 85°C (J version)K: Operating ambient temperature -40°C to 125°C (K version)ROM capacity6: 32 KB7: 48 KB8: 64 KBA: 96 KBC: 128 KBR8C/22 GroupR8C/Tiny SeriesMemory typeF: Flash memory versionRenesas MCURenesas semiconductorsFigure 1.2Type Number, Memory Size, and Package of R8C/22 GroupRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

1. Overview

Table 1.4Product Information for R8C/23 GroupCurrent of Mar. 2007

Type No.R5F21236DFP (D)R5F21237DFP (D)R5F21238DFP (D)R5F21236JFPR5F21237JFPR5F21238JFPR5F2123AJFP (D)R5F2123CJFP (D)

ROM Capacity

RAM CapacityPackage TypeRemarks

Program ROMData Flash32 Kbytes1 Kbyte X 22 KbytesPLQP0048KB-AD versionFlash

memory 48 Kbytes1 Kbyte X 22.5 KbytesPLQP0048KB-A

version64 Kbytes1 Kbyte X 23 KbytesPLQP0048KB-A

32 Kbytes1 Kbyte X 22 KbytesPLQP0048KB-AJ version48 Kbytes1 Kbyte X 22.5 KbytesPLQP0048KB-A64 Kbytes1 Kbyte X 23 KbytesPLQP0048KB-A96 Kbytes1 Kbyte X 25 KbytesPLQP0048KB-A

6 KbytesPLQP0048KB-A128 Kbytes(1)1 Kbyte X 2

1 Kbyte X 2

1 Kbyte X 21 Kbyte X 21 Kbyte X 21 Kbyte X 2

2 Kbytes2.5 Kbytes3 Kbytes5 Kbytes6 Kbytes

PLQP0048KB-AK versionPLQP0048KB-APLQP0048KB-APLQP0048KB-APLQP0048KB-A

R5F21236KFP32 KbytesR5F21237KFP48 KbytesR5F21238KFP (D)64 KbytesR5F2123AKFP (D)96 KbytesR5F2123CKFP (D)128 Kbytes(1)

NOTE:

1.Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 24. Notes on Emulator Debugger.(D): Under development

Part numberR 5 F 21 23 6 J FPPackage type:FP: PLQP0048KB-A(0.5 mm pin-pich, 7 mm square body)ClassificationD: Operating ambient temperature -40°C to 85°C (D version)J: Operating ambient temperature -40°C to 85°C (J version)K: Operating ambient temperature -40°C to 125°C (K version)ROM capacity6: 32 KB7: 48 KB8: 64 KBA: 96 KBC: 128 KBR8C/23 GroupR8C/Tiny SeriesMemory typeF: Flash memory versionRenesas MCURenesas semiconductorsFigure 1.3Type Number, Memory Size, and Package of R8C/23 GroupRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

1. Overview

1.5Pin Assignments

Figure 1.4 shows Pin Assignments (Top View).

P6_7/INT3/RXD1P6_6/INT2/TXD126P1_2/KI2/AN10Pin assignments (top view)P1_0/KI0/AN8P1_1/KI1/AN9P3_0/TRAOP3_1/TRBOP0_7/AN036353433323130292827P0_6/AN1P0_5/AN2P0_4/AN3P4_2/VREFP6_0/TREOP6_2/CRX0P6_1/CTX0P0_3/AN4P0_2/AN5P0_1/AN6P0_0/AN7P3_7/SSO37383940414243444546474810111212345678925P4_5/INT0P6_3P6_4P6_52423222120P1_3/KI3/AN11P1_4/TXD0P1_5/RXD0/(TRAIO)/(INT1)(2)P1_6/CLK0P1_7/TRAIO/INT1P2_0/TRDIOA0/TRDCLKP2_1/TRDIOB0P2_2/TRDIOC0P2_3/TRDIOD0P2_4/TRDIOA1P2_5/TRDIOB1P2_6/TRDIOC1R8C/22 Group,R8C/23 Group19181716151413P3_3/SSIP4_3P4_4P3_5/SCL/SSCKP3_4/SDA/SCSNOTES:1. P4_7 is an input-only port.2. Can be assigned to the pin in parentheses by a program.Package: PLQP0048KB-A0.5mm pin-pich, 7 mm square bodyFigure 1.4Pin Assignments (Top View)Rev.1.10Mar 16, 2007REJ03B0097-0110

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P2_7/TRDIOD1MODEP4_7/XOUTVSS/AVSSRESETP4_6/XIN(1)VCC/AVCC元器件交易网www.cecb2b.com

R8C/22 Group, R8C/23 Group

1. Overview

1.6Pin Functions

Pin Functions

Symbol

VCCVSSAVCC, AVSSRESETMODEXINXOUT

I/O Type

IIIIIO

Description

Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Applies the power supply for the A/D converter. Connect a capacitor between AVCC and AVSS.Input “L” on this pin resets the MCU.Connect this pin to VCC via a resistor.

These pins are provided for the XIN clock generationcircuit I/O. Connect a ceramic resonator or a crystaloscillator between the XIN and XOUT pins. To use anexternally derived clock, input it to the XIN pin and leavethe XOUT pin open.INT interrupt input pins.INT0 Timer RD input pins. INT1 Timer RA input pins.Key input interrupt input pins.Timer RA I/O pin.Timer RA output pin.Timer RB output pin.Timer RD I/O ports.

Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number.Table 1.5

Type

Power Supply InputAnalog Power Supply InputReset InputMODEXIN Clock InputXIN Clock Output

INT Interrupt InputINT0 to INT3I

Key Input InterruptTimer RATimer RBTimer RD

KI0 to KI3TRAIOTRAOTRBO

TRDIOA0, TRDIOA1,TRDIOB0, TRDIOB1,TRDIOC0, TRDIOC1,TRDIOD0, TRDIOD1TRDCLKTREOCLK0RXD0, RXD1TXD0, TXD1

II/OOOI/O

IOI/OIOI/OI/OI/OI/OI/OI/OIOIII/O

External clock input pin.Divided clock output pin.Transfer clock I/O pin.Serial data input pins.Serial data output pins.Clock I/O pin.Data I/O pin.Data I/O pin.

Chip-select signal I/O pin.Clock I/O pin.Data I/O pin.CAN data input pin.CAN data output pin.

Reference voltage input pin to A/D converter.Analog input pins to A/D converter.

CMOS I/O ports. Each port contains an input/outputselect direction register, allowing each pin in that port tobe directed for input or output individually.

Any port set to input can select whether to use a pull-upresistor or not by a program.

Timer RESerial Interface

I2C Bus InterfaceClock Synchronous Serial I/O with Chip Select

SCLSDASSISCSSSCKSSOCRX0CTX0

CAN Module

Reference Voltage InputVREFA/D ConverterI/O Port

AN0 to AN11P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1,

P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7P4_2, P4_6, P4_7

Input PortIInput only ports.

I: InputO: OutputI/O: Input and outputPage 8 of 48

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R8C/22 Group, R8C/23 Group

1. Overview

Table 1.6Pin Name Information by Pin Number

I/O Pin Functions for of Peripheral Modules

Clock Synchronous Serial I/O with Chip Select

Pin

Control Pin

Number123456789101112131415161718192021222324252627282930313233343536373839404142434445464748

Port

InterruptTimer

Serial InterfaceI2C Bus InterfaceSCLSDA

CAN ModuleA/D Converter

P3_5P3_3P3_4

MODE

P4_3P4_4

RESETXOUTVSS/AVSS

XINVCC/AVCC

P4_7P4_6P2_7P2_6P2_5P2_4P2_3P2_2P2_1P2_0P1_7P1_6P1_5P1_4P1_3P4_5P6_6P6_7P1_2P1_1P1_0P3_1P3_0P6_5P6_4P6_3P0_7P0_6P0_5P0_4P4_2P6_0P6_2P6_1P0_3P0_2P0_1P0_0P3_7

TRDIOD1TRDIOC1TRDIOB1TRDIOA1TRDIOD0TRDIOC0TRDIOB0TRDIOA0/TRDCLKTRAIO(TRAIO)(1)

CLK0RXD0TXD0

SSCKSSISCS

INT1(INT1)(1)KI3INT0INT2INT3KI2KI1KI0

AN11

INT0

TXD1RXD1

AN10AN9AN8

TRBOTRAO

AN0AN1AN2AN3

TREO

CRX0CTX0

AN4AN5AN6AN7

SSO

VREF

NOTE:1.Can be assigned to the pin in parentheses by a program.Rev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

2. Central Processing Unit (CPU)

2.Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FBcomprise a register bank. Two sets of register banks are provided. b31b15b8b7b0R2R3R0H (high-order of R0)R0L (low-order of R0)R1H (high-order of R1)R1L (low-order of R1)R2R3A0A1FBb19b15b0Data registers(1)Address registers(1)Frame bass registers(1)INTBHINTBLInterrupt table registerThe 4-high order bits of INTB are INTBH andthe 16-low order bits of INTB are INTBL.b19b0PCProgram counterb15b0USPISPSBb15b0User stack pointerInterrupt stack pointerStatic base registerFLGb15b8b7b0Flag registerIPLUIOBSZDCCarry flagDebug flagZero flagSign flagRegister bank select flagOverflow flagInterrupt enable flagStack pointer select flagReserved areaProcessor interrupt priority levelReserved areaNOTE:1. A register bank comprises these registers. Two sets of register banks are provided.Figure 2.1CPU RegistersRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

2. Central Processing Unit (CPU)

2.1Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.

R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. Thesame applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register(R2R0). The same applies R3R1 as R2R0.

2.2Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They alsoare used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A1 can be combined with A0 to be used a 32-bit address register (A1A0).

2.3Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4Interrupt Table Register (INTB)

INTB, a 20-bit register, indicates the start address of an interrupt vector table.

2.5Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each.The U flag of FLG is used to switch between USP and ISP.

2.7Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8Flag Register (FLG)

FLG is a 11-bit register indicating the CPU status.

2.8.1Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.

2.8.2Debug Flag (D)

The D flag is for debug only. Set to 0.

2.8.3Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.

2.8.4Sign Flag (S)

The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.

2.8.5Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.

2.8.6Overflow Flag (O)

The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.

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R8C/22 Group, R8C/23 Group

2. Central Processing Unit (CPU)

2.8.7Interrupt Enable Flag (I)

The I flag enables a maskable interrupt.

An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to0 when an interrupt request is acknowledged.

2.8.8Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of softwareinterrupt numbers. 0 to 31 is executed.

2.8.9Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10Reserved Bit

If necessary, set to 0. When read, the content is undefined.

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R8C/22 Group, R8C/23 Group

3. Memory

3.

3.1

Memory

R8C/22 Group

Figure 3.1 shows a Memory Map of R8C/22 Group. The R8C/22 Group has 1 Mbyte of address space fromaddress 00000h to FFFFFh.

The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internalROM is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of eachinterrupt routine.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5 Kbyte internalRAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also forcalling subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFR) are allocated addresses 00000h to 002FFh and 01300h to 0147Fh (SFR area forCAN). The peripheral function control registers are allocated here. All addresses within the SFR, which havenothing allocated are reserved for future user and cannot be accessed by users.

00000hSFR(Refer to 4. SpecialFunction Registers(SFRs))002FFh00400hInternal RAM0XXXXh01300h02000h03000hReserved area(1)0FFDChInternal RAM0SSSSh0YYYYhUndefined instructionOverflowBRK instructionAddress matchSingle stepWatchdog timer•oscillation stop detection•voltage detectionInternal ROM(program ROM)0FFFFhZZZZZhFFFFFhInternal ROM(3)(program ROM)Expanding area0FFFFhAddress break(Reserved)ResetNOTES:1. SFR area for CAN is allocated addresses 01300h to 0147Fh.2. The blank regions are reserved. Do not access locations in these regions.3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 24. Notes onEmulator Debugger.Internal ROMSizeAddress 0YYYYhAddress ZZZZZh08000h04000h04000h04000h04000h--13FFFh1BFFFh23FFFhSize 2 Kbytes2.5 Kbytes3 Kbytes5 Kbytes6 KbytesInternal RAMAddress 0XXXXhAddress 0SSSSh00BFFh00DFFh00FFFh00FFFh00FFFh---037FFh03BFFhPart NumberR5F21226DFP, R5F21226JFP, R5F21226KFP32 KbytesR5F21227DFP, R5F21227JFP, R5F21227KFP48 KbytesR5F21228DFP, R5F21228JFP, R5F21228KFP64 KbytesR5F2122AJFP, R5F2122AKFPR5F2122CJFP, R5F2122CKFP96 Kbytes128 KbytesFigure 3.1Memory Map of R8C/22 GroupRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

3. Memory

3.2R8C/23 Group

Figure 3.2 shows a Memory Map of R8C/23 Group. The R8C/23 Group has 1 Mbyte of address space fromaddress 00000h to FFFFFh.

The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of eachinterrupt routine.

The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyteinternal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data butalso for calling subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFR) are allocated addresses 00000h to 002FFh and 01300h to 0147Fh (SFR area forCAN). The peripheral function control registers are allocated them. All addresses within the SFR, which havenothing allocated are reserved for future use and cannot be accessed by users.

00000hSFR(Refer to 4. SpecialFunction Registers(SFRs))002FFh00400hInternal RAM0XXXXh01300h02000h02400hReserved area(2)Internal ROM(data flash)(1)0FFDCh02BFFh03000h0SSSSh0YYYYhInternal RAMInternal ROM(program ROM)Undefined instructionOverflowBRK instructionAddress matchSingle stepWatchdog timer•oscillation stop detection•voltage detection0FFFFhZZZZZhFFFFFhInternal ROM(4)(program ROM)Expanding area0FFFFhAddress break(Reserved)ResetNOTES:1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.2. SFR area for CAN is allocated addresses 01300h to 0147Fh.3. The blank regions are reserved. Do not access locations in these regions.4. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 24. Notes onEmulator Debugger.Internal ROMPart NumberInternal RAMSizeAddress 0YYYYhAddress ZZZZZhAddress 0XXXXhAddress 0SSSShSizeR5F21236DFP, R5F21236JFP, R5F21236KFP32 Kbytes-00BFFh 2 Kbytes08000h-R5F21237DFP, R5F21237JFP, R5F21237KFP48 KbytesR5F21238DFP, R5F21238JFP, R5F21238KFP64 KbytesR5F2123AJFP, R5F2123AKFPR5F2123CJFP, R5F2123CKFP96 Kbytes128 Kbytes04000h04000h04000h04000h-13FFFh1BFFFh23FFFh2.5 Kbytes3 Kbytes5 Kbytes6 Kbytes00DFFh00FFFh00FFFh00FFFh--037FFh03BFFhFigure 3.2Memory Map of R8C/23 GroupRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

4. Special Function Registers (SFRs)

4.Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Table 4.1 to Table 4.13 list the SFR Information.Table 4.1

Address0000h0001h0002h0003h0004h0005h0006h0007h0008h0009h000Ah000Bh000Ch000Dh000Eh000Fh0010h0011h0012h0013h0014h0015h0016h0017h0018h0019h001Ah001Bh001Ch001Dh001Eh001Fh0020h0021h0022h0023h0024h0025h0026h0030h0031h0032h0033h0034h0035h0036h0037h0038h0039h003FhSFR Information (1)(1)

RegisterSymbolAfter resetProcessor Mode Register 0Processor Mode Register 1System Clock Control Register 0System Clock Control Register 1PM0PM1CM0CM100h00h01101000b00100000bProtect RegisterOscillation Stop Detection RegisterWatchdog Timer Reset RegisterWatchdog Timer Start RegisterWatchdog Timer Control RegisterAddress Match Interrupt Register 0PRCROCDWDTRWDTSWDCRMAD000h00000100bXXhXXh00X11111b00h00h00h00h00h00h00h

Address Match Interrupt Enable RegisterAddress Match Interrupt Register 1AIERRMAD1Count Source Protect Mode RegisterCSPR00h10000000b(8)

High-Speed On-Chip Oscillator Control Register 0High-Speed On-Chip Oscillator Control Register 1High-Speed On-Chip Oscillator Control Register 2FRA0FRA1FRA200hValue when shipping00h

Voltage Detection Register 1(2)Voltage Detection Register 2VCA1VCA200001000b00h(3)

01000000b(4)

Voltage Monitor 1 Circuit Control RegisterVoltage Monitor 2 Circuit Control Register(5)VW1CVW2C0000X000b(3)0100X001b(4)00hX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.

2.Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.3.The LVD0ON bit in the OFS register is set to 1.

4.Power-on reset, voltage monitor 1 reset or the LVD0ON bit in the OFS register is set to 0.5.Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.6.Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7.

7.Software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6.8.The CSPROINI bit in the OFS register is 0.

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R8C/22 Group, R8C/23 Group

Table 4.2

Address0040h0041h0042h0043h0044h0045h0046h0047h0048h0049h004Ah004Bh004Ch004Dh004Eh004Fh0050h0051h0052h0053h0054h0055h0056h0057h0058h0059h005Ah005Bh005Ch005Dh005Eh005Fh0060h0061h0062h0063h0064h0065h0066h0067h0068h0069h006Ah006Bh006Ch006Dh006Eh006Fh0070h0071h0072h0073h0074h0075h0076h0077h0078h0079h007Ah007Bh007Ch007Dh007Eh007Fh 4. Special Function Registers (SFRs)

SFR Information (2)(1)

RegisterSymbolAfter resetCAN0 Wake Up Interrupt Control Register

CAN0 Successful Reception Interrupt Control RegisterCAN0 Successful Transmission Interrupt Control RegisterCAN0 State/Error Interrupt Control RegisterTimer RD0 Interrupt Control RegisterTimer RD1 Interrupt Control RegisterTimer RE Interrupt Control RegisterC01WKICC0RECICC0TRMICC01ERRICTRD0ICTRD1ICTREICXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bKey Input Interrupt Control RegisterA/D Conversion Interrupt Control RegisterSSU Interrupt Control Register/IIC Interrupt Control Register(2)UART0 Transmit Interrupt Control RegisterUART0 Receive Interrupt Control RegisterUART1 Transmit Interrupt Control RegisterUART1 Receive Interrupt Control RegisterINT2 Interrupt Control RegisterTimer RA Interrupt Control RegisterTimer RB Interrupt Control RegisterINT1 Interrupt Control RegisterINT3 Interrupt Control RegisterKUPICADICSSUIC/IICICS0TICS0RICS1TICS1RICINT2ICTRAICTRBICINT1ICINT3ICXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXX00X000bXXXXX000bXXXXX000bXX00X000bXX00X000bINT0 Interrupt Control RegisterINT0ICXX00X000bX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.

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R8C/22 Group, R8C/23 Group

Table 4.3

Address0080h0081h0082h0083h0084h0085h0086h0087h0088h0089h008Ah008Bh008Ch008Dh008Eh008Fh0090h0091h0092h0093h0094h0095h0096h0097h0098h0099h009Ah009Bh009Ch009Dh009Eh009Fh00A0h00A1h00A2h00A3h00A4h00A5h00A6h00A7h00A8h00A9h00AAh00ABh00ACh00ADh00AEh00AFh00B0h00B1h00B2h00B3h00B4h00B5h00B6h00B7h00B8h00B9h00BAh00BBh00BCh00BDh00BEh00BFh 4. Special Function Registers (SFRs)

SFR Information (3)(1)

RegisterSymbolAfter resetUART0 Transmit/Receive Mode RegisterUART0 Bit Rate Generator

UART0 Transmit Buffer RegisterUART0 Transmit/Receive Control Register 0UART0 Transmit/Receive Control Register 1UART0 Receive Buffer RegisterUART1 Transmit/Receive Mode RegisterUART1 Bit Rate RegisterUART1 Transmit Buffer RegisterUART1 Transmit/Receive Control Register 0UART1 Transmit/Receive Control Register 1UART1 Receive Buffer RegisterU0MRU0BRGU0TBU0C0U0C1U0RBU1MRU1BRGU1TBU1C0U1C1U1RB00hXXhXXhXXh

00001000b00000010bXXhXXh00hXXhXXhXXh

00001000b00000010bXXhXXh

SS Control Register H/IIC Bus Control Register 1(2)SS Control Register L/IIC Bus Control Register 2(2)SS Mode Register/IIC Bus Mode Register 1(2)SS Enable Register/IIC Interrupt Enable Register(2)SS Status Register/IIC Bus Status Register(2)SS Mode Register 2/Slave Address Register(2)SS Transmit Data Register/IIC Bus Transmit Data Register(2)SS Receive Data Register/IIC Bus Receive Data Register(2)SSCRH/ICCR1SSCRL/ICCR2SSMR/ICMRSSER/ICIERSSSR/ICSRSSMR2/SARSSTDR/ICDRTSSRDR/ICDRR00h01111101b00011000b00h00h/0000X000b00hFFhFFhX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.

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R8C/22 Group, R8C/23 Group

Table 4.4

Address00C0h00C1h00C2h00C3h00C4h00C5h00C6h00C7h00C8h00C9h00CAh00CBh00CCh00CDh00CEh00CFh00D0h00D1h00D2h00D3h00D4h00D5h00D6h00D7h00D8h00D9h00DAh00DBh00DCh00DDh00DEh00DFh00E0h00E1h00E2h00E3h00E4h00E5h00E6h00E7h00E8h00E9h00EAh00EBh00ECh00EDh00EEh00EFh00F0h00F1h00F2h00F3h00F4h00F5h00F6h00F7h00F8h00F9h00FAh00FBh00FCh00FDh00FEh00FFh 4. Special Function Registers (SFRs)

SFR Information (4)(1)

RegisterA/D RegisterADSymbolXXhXXh

After resetA/D Control Register 2A/D Control Register 0A/D Control Register 1ADCON2ADCON0ADCON100h00h00hPort P0 RegisterPort P1 RegisterPort P0 Direction RegisterPort P1 Direction RegisterPort P2 RegisterPort P3 RegisterPort P2 Direction RegisterPort P3 Direction RegisterPort P4 RegisterPort P4 Direction RegisterPort P6 RegisterPort P6 Direction RegisterP0P1PD0PD1P2P3PD2PD3P4PD4P6PD6XXhXXh00h00hXXhXXh00h00hXXh00hXXh00hUART1 Function Select RegisterU1SRXXhPort Mode RegisterExternal Input Enable RegisterINT Input Filter Select RegisterKey Input Enable RegisterPull-Up Control Register 0Pull-Up Control Register 1PMRINTENINTFKIENPUR0PUR100h00h00h00h00hXX00XX00bX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.5

Address0100h0101h0102h0103h0104h0105h0106h0107h0108h0109h010Ah010Bh010Ch010Dh010Eh010Fh0110h0111h0112h0113h0114h0115h0116h0117h0118h0119h011Ah011Bh011Ch011Dh011Eh011Fh0120h0121h0122h0123h0124h0125h0126h0127h0128h0129h012Ah012Bh012Ch012Dh012Eh012Fh0130h0131h0132h0133h0134h0135h0136h0137h0138h0139h013Ah013Bh013Ch013Dh013Eh013Fh 4. Special Function Registers (SFRs)

SFR Information (5)(1)

RegisterTimer RA Control RegisterTimer RA I/O Control RegisterTimer RA Mode RegisterTimer RA Prescaler RegisterTimer RA RegisterLIN Control RegisterLIN Status Register

Timer RB Control RegisterTimer RB One-Shot Control RegisterTimer RB I/O Control RegisterTimer RB Mode RegisterTimer RB Prescaler RegisterTimer RB Secondary RegisterTimer RB PrimarySymbolTRACRTRAIOCTRAMRTRAPRETRALINCRLINSTTRBCRTRBOCRTRBIOCTRBMRTRBPRETRBSCTRBPRAfter reset00h00h00hFFhFFh00h00h00h00h00h00hFFhFFhFFhTimer RE Counter Data Register Timer RE Compare Data RegisterTRESECTREMIN00h00hTimer RE Control Register 1Timer RE Control Register 2Timer RE Clock Source Select Register TRECR1TRECR2TRECSR00h00h00001000bTimer RD Start RegisterTimer RD Mode RegisterTimer RD PWM Mode RegisterTimer RD Function Control RegisterTimer RD Output Master Enable Register 1Timer RD Output Master Enable Register 2Timer RD Output Control RegisterTimer RD Digital Filter Function Select Register 0Timer RD Digital Filter Function Select Register 1TRDSTRTRDMRTRDPMRTRDFCRTRDOER1TRDOER2TRDOCRTRDDF0TRDDF111111100b00001110b10001000b10000000bFFh

01111111b00h00h00hX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.6

Address0140h0141h0142h0143h0144h0145h0146h0147h0148h0149h014Ah014Bh014Ch014Dh014Eh014Fh0150h0151h0152h0153h0154h0155h0156h0157h0158h0159h015Ah015Bh015Ch015Dh015Eh015Fh0160h0161h0162h0163h0164h0165h0166h0167h0168h0169h016Ah016Bh016Ch016Dh016Eh016Fh0170h0171h0172h0173h0174h0175h0176h0177h0178h0179h017Ah017Bh017Ch017Dh017Eh017Fh 4. Special Function Registers (SFRs)

SFR Information (6)(1)

RegisterTimer RD Control Register 0Timer RD I/O Control Register A0Timer RD I/O Control Register C0Timer RD Status Register 0Timer RD Interrupt Enable Register 0Timer RD PWM Mode Output Level Control Register 0Timer RD Counter 0Timer RD General Register A0Timer RD General Register B0Timer RD General Register C0Timer RD General Register D0Timer RD Control Register 1Timer RD I/O Control Register A1Timer RD I/O Control Register C1Timer RD Status Register 1

Timer RD Interrupt Enable Register 1Timer RD PWM Mode Output Level Control Register 1Timer RD Counter 1Timer RD General Register A1Timer RD General Register B1Timer RD General Register C1Timer RD General Register D1SymbolTRDCR0TRDIORA0TRDIORC0TRDSR0TRDIER0TRDPOCR0TRD0TRDGRA0TRDGRB0TRDGRC0TRDGRD0TRDCR1TRDIORA1TRDIORC1TRDSR1TRDIER1TRDPOCR1TRD1TRDGRA1TRDGRB1TRDGRC1TRDGRD1After reset00h10001000b10001000b11100000b11100000b11111000b00h00hFFhFFhFFhFFhFFhFFhFFhFFh00h10001000b10001000b11000000b11100000b11111000b00h00hFFhFFhFFhFFhFFhFFhFFhFFh

X: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.7

Address0180h0181h0182h0183h0184h0185h0186h0187h0188h0189h018Ah018Bh018Ch018Dh018Eh018Fh0190h0191h0192h0193h0194h0195h0196h0197h0198h0199h019Ah019Bh019Ch019Dh019Eh019Fh01A0h01A1h01A2h01A3h01A4h01A5h01A6h01A7h01A8h01A9h01AAh01ABh01ACh01ADh01AEh01AFh01B0h01B1h01B2h01B3h01B4h01B5h01B6h01B7h01B8h01B9h01BAh01BBh01FDh01FEh01FFh 4. Special Function Registers (SFRs)

SFR Information (7)(1)

RegisterSymbolAfter resetFlash Memory Control Register 4Flash Memory Control Register 1Flash Memory Control Register 0FMR4FMR1FMR001000000b1000000Xb00000001bX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.8

Address1300h1301h1302h1303h1304h1305h1306h1307h1308h1309h130Ah130Bh130Ch130Dh130Eh130Fh1310h1311h1312h1313h1314h1315h1316h1317h1318h1319h131Ah131Bh131Ch131Dh131Eh131Fh1320h1321h1322h1323h1324h1325h1326h1327h1328h1329h132Ah132Bh132Ch132Dh132Eh132Fh1330h1331h1332h1333h1334h1335h1336h1337h1338h1339h133Ah133Bh133Ch133Dh133Eh133Fh 4. Special Function Registers (SFRs)

SFR Information (8)(1)

Register

CAN0 Message Control Register 0CAN0 Message Control Register 1CAN0 Message Control Register 2CAN0 Message Control Register 3CAN0 Message Control Register 4CAN0 Message Control Register 5CAN0 Message Control Register 6CAN0 Message Control Register 7CAN0 Message Control Register 8CAN0 Message Control Register 9CAN0 Message Control Register 10CAN0 Message Control Register 11CAN0 Message Control Register 12CAN0 Message Control Register 13CAN0 Message Control Register 14CAN0 Message Control Register 15CAN0 Control Register CAN0 Status RegisterCAN0 Slot Status RegisterCAN0 Interrupt Control RegisterCAN0 Extended ID RegisterCAN0 Configuration RegisterCAN0 Receive Error Count RegisterCAN0 Transmit Error Count RegisterSymbolC0MCTL0C0MCTL1C0MCTL2C0MCTL3C0MCTL4C0MCTL5C0MCTL6C0MCTL7C0MCTL8C0MCTL9C0MCTL10C0MCTL11C0MCTL12C0MCTL13C0MCTL14C0MCTL15C0CTLRC0STRC0SSTRC0ICRC0IDRC0CONRC0RECRC0TECRAfter reset

00h00h00h00h00h00h00h00h00h00h00h00h00h00h00h00hX0000001bXX0X0000b00hX0000001b00h00h00h00h00h00hXXhXXh00h00hX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.9

Address1340h1341h1342h1343h1344h1345h1346h1347h1348h1349h134Ah134Bh134Ch134Dh134Eh134Fh1350h1351h1352h1353h1354h1355h1356h1357h1358h1359h135Ah135Bh135Ch135Dh135Eh135Fh1360h1361h1362h1363h1364h1365h1366h1367h1368h1369h136Ah136Bh136Ch136Dh136Eh136Fh1370h1371h1372h1373h1374h1375h1376h1377h1378h1379h137Ah137Bh137Ch137Dh137Eh137Fh 4. Special Function Registers (SFRs)

SFR Information (9)(1)

RegisterSymbolAfter resetCAN0 Acceptance Filter Support RegisterC0AFSXXhXXh

CAN0 Clock Select RegisterCAN0 Slot 0: Identifier/DLCCCLKR

CAN0 Slot 0: Data FieldCAN0 Slot 0: Time StampCAN0 Slot 1: Identifier/DLCCAN0 Slot 1: Data FieldCAN0 Slot 1: Time StampXXXX0000bXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh

X: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.10

Address1380h1381h1382h1383h1384h1385h1386h1387h1388h1389h138Ah138Bh138Ch138Dh138Eh138Fh1390h1391h1392h1393h1394h1395h1396h1397h1398h1399h139Ah139Bh139Ch139Dh139Eh139Fh13A0h13A1h13A2h13A3h13A4h13A5h13A6h13A7h13A8h13A9h13AAh13ABh13ACh13ADh13AEh13AFh13B0h13B1h13B2h13B3h13B4h13B5h13B6h13B7h13B8h13B9h13BAh13BBh13BCh13BDh13BEh13BFh 4. Special Function Registers (SFRs)

SFR Information (10)(1)

RegisterCAN0 Slot 2: Identifier/DLC SymbolXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh

After resetCAN0 Slot 2: Data FieldCAN0 Slot 2: Time StampCAN0 Slot 3: Identifier/DLC CAN0 Slot 3: Data FieldCAN0 Slot 3: Time StampCAN0 Slot 4: Identifier/DLCCAN0 Slot 4: Data FieldCAN0 Slot 4: Time StampCAN0 Slot 5: Identifier/DLC CAN0 Slot 5: Data FieldCAN0 Slot 5: Time StampX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.11

Address13C0h13C1h13C2h13C3h13C4h13C5h13C6h13C7h13C8h13C9h13CAh13CBh13CCh13CDh13CEh13CFh13D0h13D1h13D2h13D3h13D4h13D5h13D6h13D7h13D8h13D9h13DAh13DBh13DCh13DDh13DEh13DFh13E0h13E1h13E2h13E3h13E4h13E5h13E6h13E7h13E8h13E9h13EAh13EBh13ECh13EDh13EEh13EFh13F0h13F1h13F2h13F3h13F4h13F5h13F6h13F7h13F8h13F9h13FAh13FBh13FCh13FDh13FEh13FFh 4. Special Function Registers (SFRs)

SFR Information (11)(1)

RegisterCAN0 Slot 6: Identifier/DLC SymbolXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh

After resetCAN0 Slot 6: Data FieldCAN0 Slot 6: Time StampCAN0 Slot 7: Identifier/DLC CAN0 Slot 7: Data FieldCAN0 Slot 7: Time StampCAN0 Slot 8: Identifier/DLCCAN0 Slot 8: Data FieldCAN0 Slot 8: Time StampCAN0 Slot 9: Identifier/DLC CAN0 Slot 9: Data FieldCAN0 Slot 9: Time StampX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.12

Address1400h1401h1402h1403h1404h1405h1406h1407h1408h1409h140Ah140Bh140Ch140Dh140Eh140Fh1410h1411h1412h1413h1414h1415h1416h1417h1418h1419h141Ah141Bh141Ch141Dh141Eh141Fh1420h1421h1422h1423h1424h1425h1426h1427h1428h1429h142Ah142Bh142Ch142Dh142Eh142Fh1430h1431h1432h1433h1434h1435h1436h1437h1438h1439h143Ah143Bh143Ch143Dh143Eh143Fh 4. Special Function Registers (SFRs)

SFR Information (12)(1)

RegisterCAN0 Slot 10: Identifier/DLC SymbolXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh

After resetCAN0 Slot 10: Data FieldCAN0 Slot 10: Time StampCAN0 Slot 11: Identifier/DLC CAN0 Slot 11: Data FieldCAN0 Slot 11: Time StampCAN0 Slot 12: Identifier/DLCCAN0 Slot 12: Data FieldCAN0 Slot 12: Time StampCAN0 Slot 13: Identifier/DLC CAN0 Slot 13: Data FieldCAN0 Slot 13: Time StampX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/22 Group, R8C/23 Group

Table 4.13

Address1440h1441h1442h1443h1444h1445h1446h1447h1448h1449h144Ah144Bh144Ch144Dh144Eh144Fh1450h1451h1452h1453h1454h1455h1456h1457h1458h1459h145Ah145Bh145Ch145Dh145Eh145Fh1460h1461h1462h1463h1464h1465h1466h1467h1468h1469h146Ah146Bh146Ch146Dh146Eh146Fh1470h1471h1472h1473h1474h1475hFFFFh 4. Special Function Registers (SFRs)

SFR Information (13)(1)

RegisterCAN0 Slot 14: Identifier/DLC SymbolXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh

After resetCAN0 Slot 14: Data FieldCAN0 Slot 14: Time StampCAN0 Slot 15: Identifier/DLC CAN0 Slot 15: Data FieldCAN0 Slot 15: Time StampCAN0 Global Mask RegisterC0GMRCAN0 Local Mask A RegisterC0LMARCAN0 Local Mask B RegisterC0LMBROption Function Select RegisterOFS(2)X: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.

2.The OFS register cannot be changed by a program. Use a flash programmer to write to it.

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

5.Electrical Characteristics

Table 5.1

SymbolVCC/AVCCVIVOPdToprTstg

Supply voltageInput voltageOutput voltagePower dissipation

Operating ambient temperatureStorage temperature

-40°C ≤ Topr ≤ 85°C85°C < Topr ≤ 125°C

Absolute Maximum Ratings

Parameter

Condition

Rated value-0.3 to 6.5-0.3 to VCC+0.3-0.3 to VCC+0.3

300125

-40 to 85 (D, J version) /-40 to 125 (K version)

-65 to 150

UnitVVVmWmW°C°C

Table 5.2

SymbolVCC/AVCCVSS/AVCCVIHVILIOH(sum)IOH(peak)IOH(avg)IOL(sum)IOL(peak)IOL(avg)f(XIN)

Recommended Operating Conditions

Parameter

Supply voltageSupply voltageInput “H” voltageInput “L” voltagePeak sum output “H” current

Peak output “H” currentAverage output “H” currentPeak sum output “L” currents

Peak output “L” currentsAverage output “L” current

XIN clock input oscillation frequency

3.0 V ≤ VCC ≤ 5.5 V-40°C ≤ Topr ≤ 85°C3.0 V ≤ VCC ≤ 5.5 V-40°C ≤ Topr ≤ 125°C2.7 V ≤ VCC < 3.0 V

Sum of all Pins IOL (peak)Sum of all Pins IOH (peak)

Conditions

Standard

Min.2.7−0.8VCC

0−−−−−−000000−

Typ.−0−−−−−−−−−−−−−−125

Max.5.5−VCC0.2VCC-60-10-560105201610201610−

UnitVVVVmAmAmAmAmAmAMHzMHzMHzMHzMHzMHzkHz

−System clock

OCD2 = 0When XIN clock is selected.OCD2 = 1When on-chip oscillator clock is selected.

3.0 V ≤ VCC ≤ 5.5 V-40°C ≤ Topr ≤ 85°C3.0 V ≤ VCC ≤ 5.5 V-40°C ≤ Topr ≤ 125°C2.7 V ≤ VCC < 3.0 VFRA01 = 0

When low-speed on-chip oscillator clock is selected.

FRA01 = 1

When high-speed on-chip oscillator clock is selected.

3.0 V ≤ VCC ≤ 5.5 V-40°C ≤ Topr ≤ 85°CFRA01 = 1

When high-speed on-chip oscillator clock is selected.

−−20MHz

−−10MHz

NOTES:

1.VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.2.The typical values when average output current is 100 ms.

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5. Electrical Characteristics

Table 5.3

Symbol−−

A/D Converter Characteristics

Parameter

ResolutionAbsolute Accuracy

10-bit mode8-bit mode10-bit mode8-bit mode

Vref = AVCC

φAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 3.3 VφAD = 10 MHz, Vref = AVCC = 3.3 VVref = AVCC

10-bit mode8-bit mode

φAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 5.0 V

Conditions

Standard

Min.−−−−−103.32.82.700.251

Without sample & holdWith sample & hold

Typ.−−−−−−−−−−−−

Max.10±3±2±5±240−−AVCCAVCC1010

UnitBitsLSBLSBLSBLSBkΩµsµsVVMHzMHz

RladdertconvVrefVIA−

Resistor ladderConversion timeReference voltageAnalog input voltage(2)A/D operating clock frequency

NOTES:

1.VCC = AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.

2.When analog input voltage exceeds reference voltage , A/D conversion result is 3FFh in 10-bit mode, FFh in 8-bit mode.

P0P1P2P3P4P630pFFigure 5.1Ports P0 to P4, P6 Timing Measurement CircuitRev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

Table 5.4

Symbol−−−

Flash Memory (Program ROM) Electrical Characteristics

Parameter

Program/erase endurance(2)Byte program timeBlock erase time

Conditions

R8C/22 GroupR8C/23 Group

Standard

Min.100(3)1,000(3)

−−−6500−2.72.70

Ambient temperature = 55°C

20

Typ.−−500.4−−−−−−−−

Max.−−4009

97 + CPU clock × 6 cycle

−−

3 + CPU clock ×

4 cycle

5.55.560−

UnittimestimesµssµsµsnsµsVV °Cyear

td(SR-SUS)Time delay from suspend request until

erase suspend−−−−−−−

Interval from erase start/restart until following suspend request

Interval from program start/restart until following suspend request

Time from suspend until program/erase restart

Program, erase voltageRead voltage

Program, erase temperatureData hold time(7)

NOTES:

1.VCC=2.7 to 5.5 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.2.Definition of program and erase

The program and erase endurance show an erase endurance for every block. If the program and erase endurance is n times (n = 100, 1,000, 10,000), n times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on block A of 1 Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time ease.(disable overwriting).

3.Endurance to guarantee all electrical characteristics after program and erase.(1 to Min. value can be guaranteed).

4.In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram

endurance not to leave blank area as possible such as programming write addresses in turn. If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. To leave erase endurance for every block as information and determine the restricted endurance are recommended.

5.If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at

least three times until the erase error does not occur.

6.Customers desiring program/erase failure rate information should contact their Renesas technical support representative.7.The data hold time includes time that the power supply is off or the clock is not supplied.

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5. Electrical Characteristics

Table 5.5

Symbol−−−−−

Flash Memory (Data Flash Block A, Block B) Electrical Characteristics(4)

Parameter

Program/erase endurance(2)

Byte program time

(Program/erase endurance ≤ 1,000 times)Byte program time

(Program/erase endurance > 1,000 times)Block erase time

(Program/erase endurance ≤ 1,000 times)Block erase time

(Program/erase endurance > 1,000 times)

Conditions

Standard

Min.10,000(3)

−−−−−6500−2.72.7-40

Ambient temperature = 55°C

20

Typ.−50650.20.3−−−−−−−−

Max.−400−9−

97 + CPU clock × 6 cycle

−−3 + CPU clock × 4 cycle

5.55.585(8)−

UnittimesµsµsssµsµsnsµsVV °Cyear

td(SR-SUS)Time delay from suspend request until

erase suspend−−−−−−−

Interval from erase start/restart until following suspend request

Interval from program start/restart until following suspend request

Time from suspend until program/erase restart

Program, erase voltageRead voltage

Program, erase temperatureData hold time(9)

NOTES:

1.VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.2.Definition of program and erase

The program and erase endurance shows an erase endurance for every block.

If the program and erase endurance is n times (n = 100, 1,000, 10,000), n times erase can be performed for every block.For example, if performing 1-byte write to the distinct addresses on block A of 1 Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time.

However, do not perform multiple programs to the same address for one time ease (disable overwriting).

3.MInimum endurace to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed).4.Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times

are the same as that in program ROM.

5.In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram

endurance not to leave blank area as possible such as programming write addresses in turn. If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. Additionally, averaging erase endurance for block A and B can reduce effective reprogram endurance more. To leave erase endurance for every block as information and determine the restricted endurance are recommended.

6.If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at

least three times until the erase error does not occur.

7.Customers desiring program/erase failure rate information should contact their Renesas technical support representative.8. 125°C for K version.

9.The data hold time includes time that the power supply is off or the clock is not supplied.

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5. Electrical Characteristics

Suspend request(Maskable interrupt request)FMR46Fixed timeClock-dependent timetd(SR-SUS)Access restartFigure 5.2Time delay until SuspendTable 5.6

SymbolVdet1−td(E-A)Vccmin

Voltage Detection 1 Circuit Electrical Characteristics

Parameter

Voltage detection level(3)

Voltage detection circuit self power consumptionWaiting time until voltage detection circuit operation starts(2)

MCU operatingvVoltage minimum value

VCA26 = 1, VCC = 5.0 V

Condition

StandardMin.2.70−−2.70

Typ.2.850.6−−

Max.3.00−100−

UnitVµAµsV

NOTES:

1.The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (D, J version) / -40°C to 125°C (K version).2.Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

register to 0.

3.Hold Vdet2 > Vdet1.

Table 5.7

SymbolVdet2−−td(E-A)

Voltage Detection 2 Circuit Electrical Characteristics

Parameter

Voltage detection level(4)

Voltage monitor 2 interrupt request generation time(2)Voltage detection circuit self power consumptionWaiting time until voltage detection circuit operation starts(3)

VCA27 = 1, VCC = 5.0V

Condition

StandardMin.3.3−−−

Typ.3.6400.6−

Max.3.9−−100

UnitVµsµAµs

NOTES:

1.The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (D, J version) / -40°C to 125°C (K version).2.Time until the voltage monitor 2 interrupt request is generated since the voltage passes Vdet2.

3.Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2

register to 0.

4.Hold Vdet2 > Vdet1.

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5. Electrical Characteristics

Table 5.8

SymbolVpor1Vpor2trth

Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics(1)

Parameter

Power-on reset valid voltage(4)

Power-on reset or vlotage monitor 1 valid voltageExternal power Vcc rise gradient(2)

Condition

Min.−020

StandardTyp.−−−

Max.0.1Vdet1−

VVmV/msecUnit

NOTES:

1.Topr = -40°C to 85°C (D, J version) / -40°C to 125°C (K version), unless otherwise specified.2.When the condition is Vcc ≥ 1.0, this parameter is not need.

3.To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the

VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.

4.tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power

on reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for 3,000s or more if -40°C ≤ Topr < -20°C.

Vdet1(3)External power VccVpor1tw(por1)Sampling time(1, 2)Vdet1(3)trth2.7VtrthVpor2Internal reset signal(“L” valid)1× 32fOCO-S1× 32fOCO-SNOTES: 1. Hold the voltage of the MCU operation voltage range (2.7 V or above) within sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details.Figure 5.3Power-on Reset Circuit Electrical CharacteristicsRev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

Table 5.9

SymbolfOCO40MfOCO40MfOCO40MfOCO40MfOCO40MfOCO40M−−

High-Speed On-Chip Oscillator Circuit Electrical Characteristics

Parameter

High-speed on-chip oscillator frequency when the reset is deasserted

Condition

VCC = 5.0 V, Topr = 25°C

StandardMin.−39.238.838.438.037.608h

Adjust the FRA1 register to -1 bit (the value when the reset is deasserter)VCC = 5.0 V, Topr = 25°C

−

Typ.40−−−−−−+ 0.3

Max.−40.841.241.642.042.4F7h−

UnitMHzMHzMHzMHzMHzMHz−MHz

High-speed on-chip oscillator frequency temperature VCC = 4.75 V to 5.25 V,dependence0°C ≤ Topr ≤ 60°C(2)High-speed on-chip oscillator frequency temperature VCC = 3.0 V to 5.25 V,dependence-20°C ≤ Topr ≤ 85°C(2)High-speed on-chip oscillator frequency temperature VCC = 3.0 V to 5.5 V,dependence-40°C ≤ Topr ≤ 85°C(2)High-speed on-chip oscillator frequency temperature VCC = 3.0 V to 5.5 V,dependence-40°C ≤ Topr ≤ 125°C(2)High-speed on-chip oscillator frequency temperature VCC = 2.7 V to 5.5 V,dependence-40°C ≤ Topr ≤ 125°C(2)The value of the FRA1 register when the reset is deasserted

High-speed on-chip oscillator adjustment range

−−

Oscillation stability time

Self power consumption when high-speed on-chip oscillator oscillating

−−

10600

100−

µsµA

NOTES:

1.VCC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (D, J version) / -40°C to 125°C (K version), unless otherwise specified.2.The standard value shows when the reset is deasserted for the FRA1 register.

Table 5.10

SymbolfOCO-S−−

Low-Speed On-Chip Oscillator Circuit Electrical Characteristics

Parameter

Low-speed on-chip oscillator frequencyOscillation stability time

Self power consumption when low-speed on-chip oscillator oscillating

VCC = 5.0 V, Topr = 25°C

Condition

StandardMin.40−−

Typ.1251015

Max.250100−

UnitkHzµsµA

NOTE:

1.VCC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (D, J version) / -40°C to 125°C (K version), unless otherwise specified.

Table 5.11

Symboltd(P-R)td(R-S)

Power Supply Circuit Timing Characteristics

Parameter

Time for internal power supply stabilization during power-on(2)STOP exit time(3)

Condition

StandardMin.1−

Typ.−−

Max.2000150

Unitµsµs

NOTES:

1.The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless

otherwise specified.

2.Waiting time until the internal power supply generation circuit stabilizes during power-on.3.Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode.

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5. Electrical Characteristics

Table 5.12

SymboltSUCYCtHItLOtRISEtFALLtSUtHtLEADtLAGtODtSAtOR

Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)

Parameter

SSCK clock cycle timeSSCK clock “H” widthSSCK clock “L” widthSSCK clock rising timeSSCK clock falling time SSO, SSI data input setup timeSSO, SSI data input hold timeSCS setup timeSCS hold time

SSO, SSI data output delay timeSSI slave access timeSSI slave out open time

SlaveSlaveMasterSlaveMasterSlave

Conditions

Standard

Min.40.40.4−−−−10011tCYC + 501tCYC + 50

−−−

Typ.−−−−−−−−−−−−−−

Max.−0.60.61111−−−−11tCYC + 1001tCYC + 100

UnittCYC(2)tSUCYCtSUCYCtCYC(2)µstCYC(2)µsnstCYC(2)nsnstCYC(2)nsns

NOTES:

1.VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.2.1tCYC = 1/f1(s)

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5. Electrical Characteristics

4-wire bus communication mode, Master, CPHS = 1VIH or VOHSCS (output)VIH or VOHtHItFALLtRISESSCK (output)(CPOS = 1)tLOtHISSCK (output)(CPOS = 0)tLOtSUCYCSSO (output)tODSSI (input)tSUtH4-wire bus communication mode, Master, CPHS = 0SCS (output)VIH or VOHVIH or VOHtHItFALLtRISESSCK (output)(CPOS = 1)tLOtHISSCK (output)(CPOS = 0)tLOtSUCYCSSO (output)tODSSI (input)tSUtHCPHS, CPOS: Bits in SSMR registerFigure 5.4I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)Rev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

4-wire bus communication mode, Slave, CPHS = 1VIH or VOHSCS (input)VIH or VOHtLEADtHItFALLtRISEtLAGSSCK (input)(CPOS = 1)tLOtHISSCK (input)(CPOS = 0)tLOtSUCYCSSO (input)tSUtHSSI (output)tSAtODtOR4-wire bus communication mode, Slave, CPHS = 0SCS (input)VIH or VOHVIH or VOHtLEADtHItFALLtRISEtLAGSSCK (input)(CPOS = 1)tLOtHISSCK (input)(CPOS = 0)tLOtSUCYCSSO (input)tSUtHSSI (output)tSAtODtORCPHS, CPOS: Bits in SSMR registerFigure 5.5I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)Rev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

tHIVIH or VOHSSCKVIH or VOHtLOtSUCYCSSO (output)tODSSI (input)tSUtHFigure 5.6I/O Timing of Clock Synchronous Serial I/O with Chip Select(Clock Synchronous Communication Mode)

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5. Electrical Characteristics

Table 5.13

SymboltSCLtSCLHtSCLLtsftSPtBUFtSTAHtSTAStSTOPtSOAStSDAH

Timing Requirements of I2C Bus Interface(1)

Parameter

SCL input cycle timeSCL input “H” widthSCL input “L” widthSCL, SDA input falling time

SCL, SDA input spike pulse rejection timeSDA input bus-free timeStart condition input hole time

Retransmit start condition input setup timeStop condition input setup timeData input setup timeData input hold time

Conditions

Standard

Min.Typ.12tCYC +−

(2)6003tCYC +−

(2)3005tCYC +−300(2)−−

−

−−−−−−−

Max.

−

−−

Unitnsnsnsnsnsnsnsnsnsnsns

3001tCYC(2)

−

−−−−−

5tCYC(2)3tCYC(2)3tCYC(2)3tCYC(2)1tCYC + 20(2)0

NOTES:

1.VCC = 2.7 to 5.5 V, VSS = 0V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), unless otherwise specified.2.1tCYC = 1/f1(s)

VIHSDAtBUFVILtSTAHtSCLHtSTAStSPtSTOPSCLP(2)S(1)tSftSCLLtSCLSr(3)tSrtSDAHtSDASP(2)NOTES:1. Start condition2. Stop condition3. Retransmit “Start” conditionFigure 5.7I/O Timing of I2C Bus InterfaceRev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

Table 5.14

SymbolVOH

Electrical Characteristics (1) [VCC = 5 V]

Parameter

Condition

IOH = -5 mAIOH = -200 µADrive capacity HIGH

Drive capacity LOW

IOL = 5 mAIOL = 200 µADrive capacity HIGH

Drive capacity LOW

Standard

Min.Typ.VCC − 2.0−VCC − 0.3−VCC − 2.0−VCC − 2.0

−−

−−−−−

Output “H” VoltageExcept XOUTXOUT

IOH = -1 mAIOH = -500 µA

Max.

VCCVCCVCCVCC2.00.452.02.0

−

UnitVVVVVVVVV

VOLOutput “L” VoltageExcept XOUTXOUT

IOL = 1 mAIOL = 500 µA

−−

VT+-VT-Hysteresis

INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSORESET

VI = 5 V, Vcc = 5 VVI = 0 V, Vcc = 5 VVI = 0 V, Vcc = 5 V

XIN

During stop mode

0.10.5

0.1

−−

1.0

−−

−V

µAµA

IIHIIL

RPULLUPRfXINVRAMInput “H” currentInput “L” currentPull-Up ResistanceFeedback Resistance

RAM Hold Voltage

30−2.0

501.0

−

5.0-5.0167−

−

kΩMΩV

NOTE:

1.VCC = 4.2 to 5.5 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.

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5. Electrical Characteristics

Table 5.15

SymbolICC

Electrical Characteristics (2) [Vcc = 5 V]

(Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), Unless Otherwise Specified.)

Parameter

Condition

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 16 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 16MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

High-speed XIN clock offon-chip High-speed on-chip oscillator on fOCO = 10 MHzoscillator Low-speed on-chip oscillator on = 125 kHzmodeNo division

XIN clock offHigh-speed on-chip oscillator on fOCO= 10 MHzLow-speed on-chip oscillator on = 125 kHzDivide-by-8

Low-speed XIN clock offon-chip High-speed on-chip oscillator offoscillator Low-speed on-chip oscillator on = 125 kHzmodeDivide-by-8

FMR47 = 1

Wait modeXIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock operationVCA20 = 0

VCA26 = VCA27 = 0XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock offVCA20 = 0

VCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 25°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 85°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 125°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

StandardMin.Typ.Max.−12.525.0

UnitmA

Power supply current High-clock

(VCC = 3.3 to 5.5 V)modeIn single-chip mode, the output pins are open and other pins are VSS

−10.020.0mA

−6.5−mA−6.5−mA−5.0−mA

−3.5−mA

−6.513.0mA

−3.2−mA−150300µA−60120µA−3876µA−0.83.0µA−1.2−µA−4.0−µARev.1.10Mar 16, 2007REJ03B0097-0110

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5. Electrical Characteristics

Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]Table 5.16

Symboltc(XIN)tWH(XIN)tWL(XIN)

XIN input cycle timeXIN input “H” widthXIN input “L” width

XIN Input

Parameter

StandardMin.Max.50−25−25−

Unitns

nsns

Vcc = 5Vtc(XIN)tWH(XIN)XIN inputtWL(XIN)Figure 5.8Table 5.17

Symboltc(TRAIO)tWH(TRAIO)tWL(TRAIO)

XIN Input Timing Diagram when VCC = 5 VTRAIO Input

Parameter

TRAIO input cycle timeTRAIO input “H” widthTRAIO input “L” width

StandardMin.Max.100−40−40−

Unitns

nsns

Vcc = 5Vtc(TRAIO)tWH(TRAIO)TRAIO inputtWL(TRAIO)Figure 5.9TRAIO Input Timing Diagram when VCC = 5 VRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

Table 5.18

Symboltc(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)i = 0 or 1

Serial Interface

Parameter

CLK0 input cycle timeCLK0 input “H” widthCLK0 input “L” widthTXDi output delay timeTXDi hold time

RXDi input setup timeRXDi input hold time

StandardMin.Max.200−100−100−−500−50−90−

Unitns

nsnsnsnsnsns

Vcc = 5Vtc(CK)tW(CKH)CLK0tW(CKL)th(C-Q)TXDitd(C-Q)RXDitsu(D-C)th(C-D)i = 0 or 1Figure 5.10Table 5.19

SymboltW(INH)tW(INL)

Serial Interface Timing Diagram when VCC = 5 VExternal Interrupt INTi (i = 0 to 3) Input

Parameter

INTi input “H” widthINTi input “L” width

StandardMin.Max.

−250(1)250(2)

−

Unitnsns

NOTES:

1.When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either

(1/digital filter clock frequency x 3) or the minimum value of standard.

2.When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either

(1/digital filter clock frequency x 3) or the minimum value of standard.

Vcc = 5VtW(INL)INTi inputi = 0 to 3tW(INH)Figure 5.11External Interrupt INTi Input Timing Diagram when VCC = 5 VRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

Table 5.20

SymbolVOH

Electrical Characteristics (3) [VCC = 3 V]

Parameter

Condition

IOH = -1 mADrive capacity HIGH

Drive capacity LOW

IOL = 1 mADrive capacity HIGH

Drive capacity LOW

Standard

Min.Typ.VCC − 0.5−VCC − 0.5−VCC − 0.5

−

−−−−

Output “H” voltage

Except XOUT

XOUT

IOH = -0.1 mAIOH = -50 µA

Max.VCCVCCVCC0.50.50.5

−

UnitVVVVVVV

VOLOutput “L” voltage

Except XOUTXOUT

IOL = 0.1 mAIOL = 50 µA

−−

VT+-VT-Hysteresis

INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSORESET

VI = 3 V, Vcc = 3 VVI = 0 V, Vcc = 3 VVI = 0 V, Vcc = 3 V

XIN

During stop mode

0.10.3

0.1

−−

0.4

−−

−V

µAµA

IIHIIL

RPULLUPRfXINVRAMInput “H” currentInput “L” currentPull-up resistanceFeedback resistanceRAM hold voltage

66−2.01603.0−

4.0-4.0500−−

kΩMΩV

NOTE:

1.VCC = 2.7 to 3.3 V at Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.

Rev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

Table 5.21

SymbolICC

Electrical Characteristics (4) [Vcc = 3 V]

(Topr = -40 to 85°C (D, J version) / -40 to 125°C (K version), Unless Otherwise Specified.)

Parameter

Condition

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 16 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 16 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

High-speed XIN clock offon-chip High-speed on-chip oscillator on fOCO = 10 MHzoscillator Low-speed on-chip oscillator on = 125 kHzmodeNo division

XIN clock offHigh-speed on-chip oscillator on fOCO = 10 MHzLow-speed on-chip oscillator on = 125 kHzDivide-by-8

Low-speed XIN clock offon-chip High-speed on-chip oscillator offoscillator Low-speed on-chip oscillator on = 125 kHzmodeDivide-by-8

FMR47 = 1

Wait modeXIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock operationVCA20 = 0

VCA26 = VCA27 = 0XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock offVCA20 = 0

VCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 25°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 85°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

Stop modeXIN clock offTopr = 125°CHigh-speed on-chip oscillator off

Low-speed on-chip oscillator offCM10 = 1

Peripheral clock offVCA26 = VCA27 = 0

StandardMin.Typ.Max.−11.523.0

UnitmA

Power supply current High-clock

(VCC = 2.7 to 3.3 V)modeIn single-chip mode, the output pins are open and other pins are VSS

−9.519.0mA

−6.012.0mA−5.5−mA−4.5−mA

−3.0−mA

−6.312.6mA

−3.1−mA−145290µA−56112µA−3570µA−0.73.0µA−1.1−µA−3.8−µARev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

Timing Requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0V at Topr = 25°C) [VCC = 3 V]Table 5.22

Symboltc(XIN)tWH(XIN)tWL(XIN)

XIN input cycle timeXIN input “H” widthXIN input “L” width

XIN Input

Parameter

StandardMin.Max.100−40−40−

Unitns

nsns

Vcc = 3Vtc(XIN)tWH(XIN)XIN inputtWL(XIN)Figure 5.12Table 5.23

Symboltc(TRAIO)tWH(TRAIO)tWL(TRAIO)

XIN Input Timing Diagram when VCC = 3 V TRAIO Input

Parameter

TRAIO input Cycle timeTRAIO input “H” widthTRAIO input “L” width

StandardMin.Max.300−120−120−

Unitns

nsns

Vcc = 3Vtc(TRAIO)tWH(TRAIO)TRAIO inputtWL(TRAIO)Figure 5.13TRAIO Input Timing Diagram when VCC = 3 VRev.1.10Mar 16, 2007REJ03B0097-0110

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R8C/22 Group, R8C/23 Group

5. Electrical Characteristics

Table 5.24

Symboltc(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)i = 0 or 1

Serial Interface

Parameter

CLK0 input cycle timeCLK0 input “H” widthCLK0 input “L” widthTXDi output delay timeTXDi hold time

RXDi input setup timeRXDi input hold time

StandardMin.Max.300−150−150−−800−70−90−

Unitns

nsnsnsnsnsns

Vcc = 3Vtc(CK)tW(CKH)CLK0tW(CKL)th(C-Q)TXDitd(C-Q)RXDitsu(D-C)th(C-D)i = 0 or 1Figure 5.14Table 5.25

SymboltW(INH)tW(INL)

Serial Interface Timing Diagram when VCC = 3 VExternal Interrupt INTi (i = 0 to 3) Input

Parameter

INTi input “H” widthINTi input “L” width

StandardMin.Max.

−380(1)380(2)

−

Unitnsns

NOTES:

1.When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either

(1/digital filter clock frequency x 3) or the minimum value of standard.

2.When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either

(1/digital filter clock frequency x 3) or the minimum value of standard.

Vcc = 3VtW(INL)INTi inputi = 0 to 3tW(INH)Figure 5.15External Interrupt INTi Input Timing Diagram when VCC = 3 VRev.1.10Mar 16, 2007REJ03B0097-0110

Page 47 of 48

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R8C/22 Group, R8C/23 Group

Appendix 1. Package Dimensions

Appendix 1.Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages”section of the Renesas Technology website.

JEITA Package CodeP-LQFP48-7x7-0.50RENESAS CodePLQP0048KB-APrevious Code48P6Q-AMASS[Typ.]0.2gHD*1D3625NOTE)1.DIMENSIONS \"*1\" AND \"*2\"DO NOT INCLUDE MOLD FLASH.2.DIMENSION \"*3\" DOES NOTINCLUDE TRIM OFFSET.bpb1EHE3724c1*2cReferenceSymbolDimension in MillimetersMin6.96.9Nom7.07.01.48.88.89.09.09.29.21.700.170.10.220.200.090.1450.1250°8°0.50.080.100.750.750.350.51.00.650.200.20.27Max7.17.1Terminal cross section48ZE13DEA2HD1ZDIndex mark12HEAA1A2FAbpb1cA1LL1ec1ye*3cbpDetail FxxyZDZELL1Rev.1.10Mar 16, 2007REJ03B0097-0110

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REVISION HISTORY

Rev.0.100.20

DateMar 08, 2005Sep 29, 2005

R8C/22 Group, R8C/23 Group Datasheet

Description

Page−−

First Edition issued

Summary

Words standardized

- Clock synchronous serial interface → Clock synchronous serial I/O- Chip-select clock synchronous interface(SSU)

→ Clock synchronous serial I/O with chip select- I2C bus interface(IIC) → I2C bus interface

Table1.1 R8C/22 Group Performance, Table1.2 R8C/23 Group Performance

Serial Interface revised:

- Clock Synchronous Serial Interface: 1 channel

I2C bus Interface (3), Clock synchronous serial I/O with chip select- Power-On Reset Circuit added

- Power Consumption value determined

Table 1.3 Product Information of R8C/22 Group, Table 1.4 Product Information of R8C/23 GroupDate revised.

Figure 1.4 Pin AssignmentPin name revised:

- P3_5/SSCK(/SCL) → P3_5/ SCL/SSCK- P3_4/SCS(/SDA) → P3_4/ SDA /SCS- VSS → VSS/AVSS- VCC → VCC/AVCC

- P1_5/RXD0/(TRAIO/INT1) → P1_5/RXD0/(TRAIO)/(INT1)- P6_6/INT2/(TXD1) → P6_6/INT2/TXD1- P6_7/INT3/(RXD1) → P6_7/INT3/RXD1- NOTE2 added

Table 1.5 Pin Description

- Analog Power Supply Input: line added- I2C Bus Interface (IIC) → I2C Bus Interface

- SSU → Clock Synchronous Serial I/O with Chip SelectTable 1.6 Pin Name Information by Pin Number revised- Pin Number 1: (SCL) → SCL- Pin Number 2: (SDA) → SDA

- Pin Number 9: VSS → VSS/AVSS- Pin Number 11: VCC → VCC/AVCC- Pin Number 26: (TXD1) → TXD1- Pin Number 27: (RXD1) → RXD1Table 4.1 SFR Information (1) revised- 0013h: XXXXXX00b → 00h

Table 4.3 SFR Information (3) revised- 00BCh: 0000X000b → 00h/0000X000bTable 4.4 SFR Information (4) revised- 00D6h: 00000XXXb → 00h

- 00F5h: UART1 Function Select Register addedTable 4.5 SFR Information (5) revised- 0104h: TRATR → TRA

2, 3

5, 6

7

8

9

151718

19

A - 1

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REVISION HISTORY

Rev.0.20

DateSep 29, 2005

R8C/22 Group, R8C/23 Group Datasheet

Description

Page20

Summary

Table 4.6 SFR Information (6) revised- 0145h: POCR0 → TRDPOCR0- 0146h, 0147h: TRDCNT0 → TRD0- 0148h, 0149h: GRA0 → TRDGRA0- 014Ah, 014Bh: GRB0 → TRDGRB0- 014Ch, 014Dh: GRC0 → TRDGRC0- 014Eh, 014Fh: GRD0 → TRDGRD0- 0155h: POCR1 -> TRDPOCR1- 0156h, 0157h: TRDCNT1 → TRD1- 0158h, 0159h: GRA1 → TRDGRA1- 015Ah, 015Bh: GRB1 → TRDGRB1- 015Ch, 015Dh: GRC1 → TRDGRC1- 015Eh, 015Fh: GRD1 → TRDGRD15. Electrical Characteristics added

Table 1.1 Functions and Specifications for R8C/22 Group revised. NOTE1 deleted.Table 1.2 Functions and Specifications for R8C/23 Group revised. NOTE1 deleted.Table 1.3 Product Information for R8C/22 roup; \"R5F2122AJFP (D)\ \"R5F2122CKFP (D)\Figure 1.2 Type Number, Memory Size, and Package of R8C/22 Group; \"A: 96 KB\" and \"C: 128 KB\" added.Table 1.4 Product Information for R8C/23 Group; \"R5F2123AJFP (D)\ \"R5F2123CKFP (D)\Figure 1.3 Type Number, Memory Size, and Package of R8C/23 Group; \"A: 96 KB\" and \"C: 128 KB\" added.Figure 3.1 Memory Map of R8C/22 Group revised.Figure 3.2 Memory Map of R8C/23 Group revised.Table 4.1 SFR Information (1)(1); NOTE8; \"The CSPROINI bit in the OFS register is set to 0.\" → \"The CSPROINI bit in the OFS register is 0.\" revised.Table 5.1 Absolute Maximum Ratings; Power dissipation revised.Table 5.2 Recommended Operating Conditions; System clock revised.Table 5.8 Voltage Monitor 1 Reset Circuit Electrical Characteristics → Table 5.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics(1) replaced.Table 5.8 revised.NOTE3 added.Table 5.9 Power-on Reset Circuit Electrical Characteristics deleted.Figure 5.3 Power-on Reset Circuit Electrical Characteristics revised.Table 5.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics → Table 5.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics revised.A - 2

28

1.00

Oct 27, 2006

235

All pages\"Preliminary\" and \"Under development\" deleted6

131415

2833

34

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REVISION HISTORY

Rev.1.00

DateOct 27, 2006

R8C/22 Group, R8C/23 Group Datasheet

Description

Page40

Summary

Table 5.15 Electrical Characteristics (1) [VCC = 5 V] → Table 5.14 Electrical Characteristics (1) [VCC = 5 V] revised. RAM Hold Voltage, Min.; \"1.8\" → \"2.0\" corrected.Table 5.16 Electrical Characteristics (2) [Vcc = 5 V] → Table 5.15 Electrical Characteristics (2) [Vcc = 5 V] revised. Wait mode revised.Table 5.21 Electrical Characteristics (3) [VCC = 3 V → Table 5.20 Electrical Characteristics (3) [VCC = 3 V] revised. RAM hold voltage, Min.; \"1.8\" → \"2.0\" corrected.Table 5.22 Electrical Characteristics (4) [Vcc = 3 V] → Table 5.21 Electrical Characteristics (4) [Vcc = 3 V] revised. Wait mode revised.D version products added.Relevant descriptions revised because of expanding products- Table 1.1 to 1.4 revised.- Figure 1.2 and 1.3 revised.- Figure 3.1 and 3.2 revised.- Table 5.1 to 5.15 revised.- Table 5.20 and 5.21 revised.Table 4.1 revised; 000Ah: “00XXX000b” → “00h”, 000Fh: “00011111b” → “00X11111b”Table 5.17 and Figure 5.9 revised; “INT1 input” deleted.Table 5.19 and Figure 5.11 revised; “i = 0, 2, 3” → “i = 0 to 3”Table 5.23 and Figure 5.13 revised; “INT1 input” deleted.Table 5.25 and Figure 5.15 revised; “i = 0, 2, 3” → “i = 0 to 3”41

44

45

1.10Mar 16, 2007−

15

42434647

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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanNotes:1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations.4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document.6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges.10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment.12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICESRefer to \"http://www.renesas.com/en/network\" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900http://www.renesas.comRenesas Technology (Shanghai) Co., Ltd.Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001Renesas Technology Korea Co., Ltd.Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, KoreaTel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. BhdUnit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, MalaysiaTel: <603> 7955-9390, Fax: <603> 7955-9510© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.

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