IS61LV5128资料

IS61LV5128FEATURES

512K x 8 HIGH-SPEED CMOS STATIC RAM

󰀁High-speed access times:󰀑 8, 10, 12 and 15 ns

󰀁High-preformance, lower-power CMOS process󰀁Multiple center power and ground pins forgreater noise immunity

󰀁Easy memory expansion with CE and OEoptions

󰀁CE power-down

󰀁Fully static operation: no clock or refreshreguired

󰀁TTL compatible inputs and outputs󰀁Single 3.3V + 10% power supply󰀁Packages available:󰀑 36-pin 400mil SOJ󰀑 44-pin TSOP-2

524,288-word by 8-bit COMS static RAM. The IS61LV5128 isfabricated using 1+51's high-performance CMOS technology.This highly reliable process coupled with innovative circuitdesign techniques, yields higher preformance and low powerconsumotion devices.

When CE is HIGH (deselected), the device assumes a standbymode at which the power dissipation can be reduced down to250 µW (typical) with CMOS input levels.

The IS61LV5128 operates from a single 3.3V power supplyand all inputs are TTL-compatible.

The IS61LV5128 is available in 36-pin, 400mil SOJ and 44-pinTSOP-2 package.

DESCRIPTION

The 1+51 IS61LV5128 is a very high-speed, low power,

FUNCTIONAL BLOCK DIAGRAM

A0-A18DECODER512K X 8MEMORY ARRAYVCCGNDI/ODATACIRCUITI/O0-I/O7COLUMN I/OCEOEWECONTROLCIRCUITICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errorswhich may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

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IS61LV5128

PIN CONFIGURATION

36-Pin SOJ

A0A1A2A3A4CEI/O0I/O1VccGNDI/O2I/O3WEA5A6A7A8A9123456789101112131415161718363534333231302928272625242322212019NCA18A17A16A15OEI/O7I/O6GNDVccI/O5I/O4A14A13A12A11A10NCPIN CONFIGURATION

44-Pin TSOP-2NCNCA0A1A2A3A4CEI/O0I/O1VccGNDI/O2I/O3WEA5A6A7A8A9NCNC1234567891011121314151617181920212244434241403938373635343332313029282726252423NCNCNCA18A17A16A15OEI/O7I/O6GNDVccI/O5I/O4A14A13A12A11A10NCNCNCPIN DESCRIPTIONS

A0-A18CEOEWEI/O0-I/O7VccGNDNC

Address InputsChip Enable InputOutput Enable InputWrite Enable InputInput/OutputPowerGroundNo Connection

TRUTH TABLE

Mode

Not Selected(Power-down)Output DisabledReadWrite

WEXHHL

CEHLLL

OEXHLX

I/O Operation

High-ZHigh-ZDOUTDIN

Vcc CurrentISB󰀁, ISB

ICCICCICC

ABSOLUTE MAXIMUM RATINGS(1)

SymbolVTERMTBIASTSTGPD

Parameter

Terminal Voltage with Respect to GNDTemperature Under BiasStorage TemperaturePower DissipationValueUnit󰀾0.5 to Vcc + 0.5V󰀾55 to +125°C󰀾65 to +150°C

1.0WNotes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at these or anyother conditions above those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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IS61LV5128

OPERATING RANGE

Range

CommercialIndustrial

Ambient Temperature

0°C to +70°C󰀾40°C to +85°C

VCC

3.3V + 10%3.3V + 10%DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SymbolVOHVOLVIHVILILIILO

Parameter

Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW Voltage󰀁󰀂󰀃Input LeakageOutput Leakage

GND ≤ VIN ≤ VCC

GND ≤ VOUT ≤ VCC, Outputs Disabled

Com.Ind.Com.Ind.

Test Conditions

VCC = Min., IOH = 󰀾4.0 mAVCC = Min., IOL = 8.0 mA

Min.2.4󰁄2.0󰀾0.3󰀾1󰀾5󰀾1󰀾5

Max.󰁄0.4VCC + 0.30.81515

UnitVVVVµAµA

Notes:

1.VIL = 󰀩3.0V for pulse width less than 10 ns.

2.The Vcc operating range for 8 ns is 3.3V +10%, -5%.

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

SymbolICCISB󰀁ParameterVcc Dynamic OperatingSupply CurrentTTL Standby Current(TTL Inputs)CMOS StandbyCurrent (CMOS Inputs)Test ConditionsVCC = Max.,IOUT = 0 mA, f = fMAXVCC = Max.,VIN = VIH or VILCE ≥ VIH , f = 0VCC = Max.,CE ≥ VCC 󰀾 0.2V,VIN ≥ VCC 󰀾 0.2V, orVIN ≤ 0.2V, f = 0Com.Ind.Com.Ind.Com.Ind.-8 nsMin.Max.󰁄󰁄󰁄󰁄󰁄󰁄30031055651015-10 nsMin.Max.󰁄󰁄󰁄󰁄󰁄󰁄28029055651015-12 nsMin.Max.󰁄󰁄󰁄󰁄󰁄󰁄26027055651015-15 nsMin.Max.󰁄󰁄󰁄󰁄󰁄󰁄24025055651015UnitmAmAISB mANote:

1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

CAPACITANCE(1,2)

SymbolCINCOUT

ParameterInput CapacitanceOutput Capacitance

ConditionsVIN = 0VVOUT = 0V

Max.68

UnitpFpF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.

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IS61LV5128

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

SymbolParameterRead Cycle TimeAddress Access TimeOutput Hold TimeCE Access TimeOE Access TimeMin.8󰁄3󰁄󰁄0003-8Max.󰁄8󰁄844󰁄4󰁄-10Min.Max.10󰁄3󰁄󰁄󰁄003󰁄10󰁄1055󰁄5󰁄-12Min.Max.12󰁄3󰁄󰁄󰁄003󰁄12󰁄1266󰁄6󰁄-15Min.Max.15󰁄 3󰁄󰁄0003󰁄15󰁄1576󰁄6󰁄UnitnsnsnsnsnsnsnsnsnstRCtAAtOHAtACEtDOEtHZOE󰀁 󰀃OE to High-Z OutputtLZOE󰀁 󰀃OE to Low-Z OutputtHZCE󰀁 CE to High-Z OutputtLZCE󰀁 󰀃CE to Low-Z OutputNotes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of0 to 3.0V and output loading specified in Figure 1a.

2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.3.Not 100% tested.

AC TEST CONDITIONS

ParameterInput Pulse Level

Input Rise and Fall TimesInput and Output Timingand Reference LevelsOutput Load

Unit0V to 3.0V3 ns1.5VSee Figures 1 and 2

Notes:

1.The Vcc operating range for 8 ns is 3.3V +10%, -5%.

AC TEST LOADS

319 Ω3.3V3.3V319 ΩOUTPUT30 pFIncludingjig andscope353 ΩOUTPUT5 pFIncludingjig andscope353 ΩFigure 1.

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Figure 2.

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IS61LV5128

AC WAVEFORMSREAD CYCLE NO. 1(1,2)

t RCADDRESSt AAt OHADOUTPREVIOUS DATA VALIDt OHADATA VALIDREAD CYCLE NO. 2(1,3)

t RCADDRESSt AAOEt OHAt HZOEt DOECEt LZOEt LZCEt ACEDATA VALIDt HZCEDOUTHIGH-ZNotes:

1.WE is HIGH for a Read Cycle.

2.The device is continuously selected. OE, CE = VIL.

3.Address is valid prior to or coincident with CE LOW transitions.

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IS61LV5128

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

SymbolParameterWrite Cycle TimeCE to Write EndAddress Setup Timeto Write EndAddress Hold from Write EndAddress Setup TimeWE Pulse WidthData Setup to Write EndData Hold from Write End-8Min.Max.8770074.50󰁄3󰁄󰁄󰁄󰁄󰁄󰁄󰁄󰁄4󰁄-10Min.Max.108800850󰁄3󰁄󰁄󰁄󰁄󰁄󰁄󰁄󰁄5󰁄-12Min.Max.129900960󰁄3󰁄󰁄󰁄󰁄󰁄󰁄󰁄󰁄6󰁄-15Min.Max.151010001070󰁄3󰁄󰁄󰁄󰁄󰁄󰁄󰁄󰁄7󰁄UnitnsnsnsnsnsnsnsnsnsnstWCtSCEtAWtHAtSAtPWEtSDtHDtHZWE󰀁 󰀃WE LOW to High-Z OutputtLZWE󰀁 󰀃WE HIGH to Low-Z OutputNotes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V andoutput loading specified in Figure 1a.

2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3.The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or fallingedge of the signal that terminates the write.

AC WAVEFORMS

WRITE CYCLE NO. 1󰀅 (1,2)(CE Controlled, OE is HIGH or LOW)t WCADDRESSVALID ADDRESSt SACEt SCEt AWt PWE1t PWE2t HZWEt HAWEt LZWEHIGH-ZDOUTDATA UNDEFINEDt SDDINt HDDATAIN VALID6Integrated Circuit Solution, Inc.

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IS61LV5128

WRITE CYCLE NO. 2 (1,2)󰀅(WE Controlled, OE is HIGH During Write Cycle)t WCADDRESSVALID ADDRESSt HAOECELOWt AWt PWE1WEt SADOUTDATA UNDEFINEDt HZWEHIGH-Zt LZWEt SDDINt HDDATAIN VALIDWRITE CYCLE NO. 3󰀅(WE Controlled, OE is LOW During Write Cycle)t WCADDRESSVALID ADDRESSOECELOWt HALOWt AWt PWE2WEt SADOUTDATA UNDEFINEDt HZWEHIGH-Zt LZWEt SDDINt HDDATAIN VALIDNotes:1.The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or fallingedge of the signal that terminates the Write.2.I/O will assume the High-Z state if OE > VIH.

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IS61LV5128

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)8101215Order Part No.IS61LV5128-8TIS61LV5128-8KIS61LV5128-10TIS61LV5128-10KIS61LV5128-12TIS61LV5128-12KIS61LV5128-15TIS61LV5128-15KPackage400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJORDERING INFORMATION

Industrial Range: 󰀰40°C to +85°C

Speed (ns)8101215Order Part No.IS61LV5128-8TIIS61LV5128-8KIIS61LV5128-10TIIS61LV5128-10KIIS61LV5128-12TIIS61LV5128-12KIIS61LV5128-15TIIS61LV5128-15KIPackage400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2400mil SOJHEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333Fax: 886-3-5783000

Integrated Circuit Solution, Inc.

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140FAX: 886-2-26962252http://www.icsi.com.tw

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