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cd4013BCM

来源:知库网
CD4013BC Dual D-Type Flip-FlopOctober 1987Revised January 1999

CD4013BC

Dual D-Type Flip-Flop

General Description

The CD4013B dual D-type flip-flop is a monolithic comple-mentary MOS (CMOS) integrated circuit constructed withN- and P-channel enhancement mode transistors. Eachflip-flop has independent data, set, reset, and clock inputsand “Q” and “Q” outputs. These devices can be used forshift register applications, and by connecting “Q” output tothe data input, for counter and toggle applications. Thelogic level present at the “D” input is transferred to the Qoutput during the positive-going transition of the clockpulse. Setting or resetting is independent of the clock andis accomplished by a high level on the set or reset linerespectively.

Features

sWide supply voltage range: 3.0V to 15VsHigh noise immunity:

compatibility:

0.45 VDD (typ.)

sLow power TTL:fan out of 2 driving 74L

or 1 driving 74LS

Applications

•Automotive•Data terminals•Instrumentation•Medical electronics•Alarm system•Industrial electronics•Remote metering•Computers

Ordering Code:

Order NumberCD4013BCMCD4013BCSJCD4013BCN

Package Number

M14AM14DN14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC and SOP

Truth Table

CL(Note 1)

D01xxxx

R000101

S000011

Q01Q011

Q10Q101

󰀑󰀑󰀐xxx

No Change

x = Don't Care Case

Note 1: Level Change

Top View

© 1999 Fairchild Semiconductor CorporationDS005946.prfwww.fairchildsemi.com

CD4013BCSchematic Diagrams

Logic Diagram

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CD4013BC Absolute Maximum Ratings(Note 2)

(Note 3)

DC Supply Voltage (VDD)Input Voltage (VIN)

Storage Temperature Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)

260°C700 mW500 mW

−0.5 VDC to +18 VDC−0.5 VDC to VDD +0.5 VDC

−65°C to +150°C

Recommended OperatingConditions (Note 3)

DC Supply Voltage (VDD)Input Voltage (VIN)

Operating Temperature Range (TA)

+3 VDC to +15 VDC0VDC to VDD VDC−40°C to +85°C

Note 2: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed, they are not meant to imply thatthe devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device operation.

Note 3: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

SymbolIDD

Parameter

Quiescent DeviceCurrent

VOL

LOW LevelOutput Voltage

Conditions

VDD = 5V, VIN = VDD or VSSVDD = 10V, VIN = VDD or VSSVDD = 15V, VIN = VDD or VSS|IO| < 1.0 µAVDD = 5VVDD = 10VVDD = 15V

VOH

HIGH LevelOutput Voltage

|IO| < 1.0 µAVDD = 5VVDD = 10VVDD = 15V

VIL

LOW LevelInput Voltage

|IO| < 1.0 µA

VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V

VIH

HIGH LevelInput Voltage

|IO| < 1.0 µA

VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V

IOL

LOW Level OutputCurrent (Note 4)

IOH

HIGH Level OutputCurrent (Note 4)

IIN

Input Current

VDD = 5V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVDD = 5V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15V

Note 4: IOH and IOL are measured one output at a time.

−40°CMin

Max4.08.016.00.050.050.05

4.959.9514.95

1.53.04.0

3.57.011.00.521.33.6−0.52−1.3−3.6

−0.30.3

3.57.011.00.441.13.0−0.44−1.1−3.04.959.9514.95Min

+25°CTyp

Max4.08.016.00.050.050.05

+85°CMin

Max30601200.050.050.05

4.959.9514.95

1.53.04.0

1.53.04.0

UnitsµAµAµAVVVVVVVVVVVVmAmAmAmAmAmA

3.57.011.0

0.882.258.8−0.88−2.25−8.8−10−510−5

−0.30.3

0.360.92.4−0.36−0.9−2.4

−1.01.0

µAµA

3www.fairchildsemi.com

CD4013BCAC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise noted

SymbolCLOCK OPERATIONtPHL, tPLH

Propagation Delay Time

VDD = 5VVDD = 10VVDD = 15V

tTHL, tTLH

Transition Time

VDD = 5VVDD = 10VVDD = 15V

tWL, tWH

Minimum ClockPulse Width

tRCL, tFCL

Maximum Clock Rise andFall Time

tSU

Minimum Set-Up Time

VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V

fCL

Maximum ClockFrequency

SET AND RESET OPERATIONtPHL(R),tPLH(S)tWH(R),tWH(S)CIN

Minimum Set andReset Pulse WidthAverage Input CapacitancePropagation Delay Time

VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VAny Input

Note 5: AC Parameters are guaranteed by DC correlated testing.

ParameterConditionsMinTypMaxUnits

200806510050401004032

35016012020010080200806515105

nsnsnsnsnsnsnsnsnsµsµsµsnsnsnsMHzMHzMHz

201512

2.56.27.6

512.515.515065459040255

403025

VDD = 5VVDD = 10VVDD = 15V

3001309018080507.5

nsnsnsnsnsnspF

Switching Time Waveforms

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CD4013BC Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

5www.fairchildsemi.com

CD4013BC Dual D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:

2.A critical component in any component of a life support1.Life support devices or systems are devices or systems

device or system whose failure to perform can be rea-which, (a) are intended for surgical implant into the

sonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failure

device or system, or to affect its safety or effectiveness.to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to thewww.fairchildsemi.comuser.

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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