Internal clock signal generation circuit including

专利名称：Internal clock signal generation circuit

including delay line, and synchronous typesemiconductor memory device includinginternal clock signal

发明人：Hisashi Iwamoto,Yasumitsu Murai申请号：US09/012558申请日：19980123公开号：US05946268A公开日：19990831

摘要：An internal clock generation circuit includes a delay line in which a plurality ofinverter circuits are connected in series. A switch and a capacitor are connected to anoutput node of each inverter circuit. The switch connected to each inverter circuit isturned on/off individually according to respective control signals. In response to theswitch being turned on, the output node of a corresponding inverter circuit and thecapacitor are connected, whereby the capacitance of the output node of the

corresponding inverter circuit is altered. As a result, the transmission rate of the signal isaltered.

申请人：MITSUBISHI DENKI KABUSHIKI KAISHA,MITSUBISHI ELECTRIC ENGINEERINGCOMPANY LIMITED

代理机构：McDermott, Will & Emery

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