专利名称：Method for evaluating semiconductor device发明人：Etsuko Asano,Kiyoshi Kato,Yutaka
Shionoiri,Masahiko Hayakawa
申请号：US11132434申请日：20050519
公开号：US20050273290A1公开日：20051208
专利附图：
摘要：The present invention provides a method for evaluating an intended element ora parameter. In addition, the invention provides an evaluation method for obtaining amore precise result rapidly. According to the invention, a plurality of evaluation circuits
are formed over the same substrate, and while simultaneously operating the plurality ofevaluation circuits, an output of one evaluation circuit selected by a selection circuit thatis formed over the substrate is arbitrarily evaluated.
申请人：Etsuko Asano,Kiyoshi Kato,Yutaka Shionoiri,Masahiko Hayakawa
地址：Atsugi JP,Sagamihara JP,Isehara JP,Atsugi JP
国籍：JP,JP,JP,JP
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