Data Sheet No. PD60238 revE
IRS2153(1)D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Integrated 600 V half-bridge gate driver CT, RT programmable oscillator 15.4 V Zener clamp on VCC Micropower startup
Non-latched shutdown on CT pin (1/6th VCC) Internal bootstrap FET
Excellent latch immunity on all inputs and outputs +/- 50 V/ns dV/dt immunity ESD protection on all pins 8-lead SOIC or PDIP package Internal deadtime
VOFFSET Duty cycle Driver source/sink
current
Vclamp Deadtime
600 V Max 50%
180 mA/260 mA typ.
15.4 V typ.
1.1 µs typ. (IRS2153D) 0.6 µs typ. (IRS21531D)
Features Product Summary
Description
The IRS2153(1)D is based on the popular IR2153 self-oscillating half-bridge gate driver IC using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable rugged monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers.
Package PDIP8 SO8
IRS2153(1)DPbF IRS2153(1)DSPbF
Typical Connection Diagram + AC Rectified LineRVCCVCC18VBCBOOTMHSIRS2153(1)DRT27HORTCTCVCCCTCOM36VSLRL45LOMLS- AC Rectified Line 1
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IRS2153(1)D
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Parameter Symbol Definition Min. Max. Units
VB VS VHO VLO IRT VRT VCT ICC IOMAX dVS/dt PD PD RthJA RthJA TJ TS TL
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage RT pin current RT pin voltage CT pin voltage
Supply current (Note 1)
Maximum allowable current at LO and HO due to external power transistor Miller effect. Allowable offset voltage slew rate
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin DIP Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin SOIC Thermal resistance, junction to ambient, 8-Pin DIP Thermal resistance, junction to ambient, 8-Pin SOIC Junction temperature Storage temperature
Lead temperature (soldering, 10 seconds)
-0.3 VB - 25 VS – 0.3 -0.3 -0.3 -0.3 ---
625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
20
V
-5 5 mA
V
mA
-500 500 -50
50
V/ns
--- 1.0
W --- 0.625 --- --- -55 -55 ---
85 128 150 150 300
ºC ºC/W
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal
breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
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IRS2153(1)D
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter Symbol Definition Min. Max. Units
VBS VS VCC ICC TJ
Note 2: It is recommended to avoid output switching conditions where the negative-going spikes at the VS
node would decrease VS below ground by more than -5 V. Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6 V zener diode
clamping the voltage at this pin.
High side floating supply voltage
Steady state side floating supply offset voltage Supply voltage Supply current Junction temperature
VCC - 0.7 -3.0 (Note 2) VCCUV+ +0.1 V
(Note 3) -40
VCLAMP 600 VCC CLAMP
5 125
V mA ºC
Recommended Component Values
Parameter Symbol Component Min. Max. Units
RT CT
Timing resistor value CT pin capacitor value
kΩ
330 --- pF
1
---
VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO = CHO = 1 nF.
Frequency vs. RT1,000,000CT Values100,000Frequency (Hz)10,0001,000100101,000330pf470pF1nF2.2nF4.7nF10nF10,000100,0001,000,000RT (Ohm)For further information, see Fig. 12.
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IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 °C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Test Conditions Symbol Definition Min Typ Max Units Low Voltage Supply Characteristics
VCCUV+ Rising VCC undervoltage lockout threshold VCCUV- Falling VCC undervoltage lockout threshold VCCUVHYS VCC undervoltage lockout hysteresis IQCCUV ICC
Micropower startup VCC supply current VCC supply current
IQCC Quiescent VCC supply current VCC CLAMP VCC zener clamp voltage Floating Supply Characteristics IQBS Quiescent VBS supply current VBSUV+ VBSUV- ILK
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going threshold
Offset supply leakage current
---
60
80
µA
10.0 8.0 1.6 --- --- --- 14.4
11.0 9.0 2.0 130 800 1.8 15.4
12.0 10.0 2.4 170 1000 --- 16.8
V µA mA V
VCC ≤ VCCUV-
RT = 36.9 kΩ ICC = 5 mA
8.0 9.0 9.5 V
7.0 8.0 9.0 ---
---
50
µA
VB = VS = 600 V RT = 36.5 kΩ RT = 7.15 kΩ
fo < 100 kHz
VCC = 7 V
Oscillator I/O Characteristics fOSC
Oscillator frequency
18.4 19.0 19.6 --- --- 0.20 --- --- 2.2
50
0.02
kHz
88 93 100 --- 1.0 0.6 --- --- 2.4
V % µA mA
d RT pin duty cycle ICT
CT pin current
ICTUV UV-mode CT pin pulldown current VCT+ Upper CT ramp voltage threshold VCT- Lower CT ramp voltage threshold VCTSD
CT voltage shutdown threshold
0.30 9.32 4.66 2.3
VRT+ High-level RT output voltage, VCC - VRT VRT- Low-level RT output voltage VRTUV UV-mode RT output voltage
--- 10 50 --- 100 300 --- 10 50 --- 100 300 --- 0 100
mV
--- 10 50 --- 100 300
IRT = -100 µA IRT = -1 mA IRT = 100 µA IRT = 1 mA VCC ≤ VCCUV- IRT = -100 µA,
VCT = 0 V
VRTSD SD-mode RT output voltage, VCC - VRT
IRT = -1 mA,
VCT = 0 V
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IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 °C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol Definition Min
Gate Driver Output Characteristics VOH VOL VOL_UV tr tf tsd td td IO+ IO-
High-level output voltage Low-level output voltage UV-mode output voltage Output rise time Output fall time
Shutdown propagation delay
Output deadtime (HO or LO) (IRS2153D) Output deadtime (HO or LO) (IRS21531D) Output source current Output sink current
--- --- --- --- --- --- 0.65 0.35 --- ---
Test Conditions Typ Max Units VCC COM COM 120 50 350 1.1 0.6 180 260
--- --- --- 220 80 --- 1.75 0.85 --- ---
µs µs mA ns V
IO = 0 A IO = 0 A, VCC ≤ VCCUV-
Bootstrap FET Characteristics VB_ON IB_CAP IB_10V
5
VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on
--- 40 10
13.7 55 12
--- --- ---
V mA
CBS=0.1 uF VB=10 V
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IRS2153(1)D
Lead Definitions
VCC18VBIRS2153(1)DRT27HOCT36VSCOM45LO
Lead
Symbol Description VCC RT CT COM LO VS HO VB
Logic and internal gate drive supply voltage Oscillator timing resistor input Oscillator timing capacitor input IC power and signal ground Low-side gate driver output High voltage floating supply return High-side gate driver output High side gate driver floating supply
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IRS2153(1)D
Functional Block Diagram
RT28VBR+HVQ-LEVELSHIFTPULSER7HORFILTERSRQDEADTIMEPULSE6VS+GENBOOTSTRAP-SQDRIVER/2DEADTIME15.4V1VCC+SQDELAY5LOCT3-R1R2R/24COMM1DETECTUV 7
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IRS2153(1)D
Timing Diagram
Operating Mode
VCCUV+VCC
Fault Mode: 2/3 VCCCT <1/6*VCC VCT
1/3 VCC1/6 VCCVCCLO
DTVCCHO
DTVCCVRT
IRT
Switching Time Waveform Deadtime Waveform
90%trtfLO10%DTLODTHO90%HO90%HOLO10% 10%
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IRS2153(1)D
Functional Description
Bootstrap MOSFET
The internal bootstrap FET and supply capacitor (CBOOT) comprise Under-voltage Lock-Out Mode (UVLO)
the supply voltage for the high side driver circuitry. The internal The under-voltage lockout mode (UVLO) is defined as the state boostrap FET only turns on when LO is high. To guarantee that
the IC is in when Vthe high-side supply is charged up before the first pulse on pin CC is below the turn-on threshold of the IC. The IRS2153(1)D under voltage lock-out is designed to maintain an HO, the first pulse from the output drivers comes from the LO pin. ultra low supply current of less than 170 µA, and to guarantee the IC is fully functional before the high and low side output drivers
are activated. During under voltage lock-out mode, the high and
Normal operating mode low-side driver outputs HO and LO are both low.
Once the VCCUV+ threshold is passed, the MOSFET M1 opens, RT
increases to approximately VCC (VCC-VRT+) and the external CT
Supply voltage capacitor starts charging. Once the CT voltage reaches VCT-
(about 1/3 of VCC), established by an internal resistor ladder, LO + AC Rectified Lineturns on with a delay equivalent to the deadtime (td). Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO goes low, RT
RVCCgoes down to approximately ground (VRT-), the CT capacitor discharges and the deadtime circuit is activated. At the end of the
VCC18VBdeadtime, HO goes high. Once the CT voltage reaches VCT-, HO DCBOOTgoes low, RT goes high again, the deadtime is activated. At the
RT)MHS1end of the deadtime, LO goes high and the cycle starts over 2(7HO3again.
RT5L CT1VS2The following equation provides the oscillator frequency: CVCC36CTSRL COM4RI5LOMLSf~
1
1.453×RT×CT
- AC Rectified Line Fig. 1 Typical Connection Diagram
This equation can vary slightly from actual measurements due to
internal comparator over- and under-shoot delays. For a more Fig. 1 shows an example of supply voltage. The start-up capacitor accurate determination of the output frequency, the frequency (CVCC) is charged by current through supply resistor (RVCC) minus characteristic curves should be used (RT vs. Frequency, page 3).
the start-up current drawn by the IC. This resistor is chosen to provide sufficient current to supply the IRS2153(1)D from the DC
bus. CVCC should be large enough to hold the voltage at Vcc Shut-down
above the UVLO threshold for one half cycle of the line voltage as If CT is pulled down below VCTSD (approximately 1/6 of VCC) by it will only be charged at the peak, typically 0.1 uF. It will be an external circuit, CT doesn’t charge up and oscillation stops. necessary for RVCC to dissipate around 1 W.
LO is held low and the bootstrap FET is off. Oscillation will
resume once CT is able to charge up again to VCT-. The use of a two diode charge pump made of DC1, DC2 and CVS (Fig. 2) from the half bridge (VS) is also possible however
the above approach is simplest and the dissipation in RVCC should not be unacceptably high.
+ AC Rectified LineRVCCVCCVB18CBOOTDRTMHS2)17HO(DC2RT3LCT356VSCVCC1CT2CVSSRLCOM4R5LOMLSDC1I- AC Rectified LineFig. 2 Charge pump circuit
The supply resistor (RVCC) must be selected such that enough supply current is available over all operating conditions.
Once the capacitor voltage on VCC reaches the start-up threshold VCCUV+, the IC turns on and HO and LO begin to oscillate.
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IRS2153(1)D
1910018.898))zHzHkk(18.6( 96 yycncneeuuqe18.4qe94rrFF9218.29018-250255075100125111213141516Temperature(C)VCC(V)FREQ vs VCC FREQ vs TEMPFig. 3 Fig. 4
1.41.251.31.15)S1.05S)1.2uu((TTD1.1D0.9510.850.90.75111213141516-250255075100125VCC(V)Temperature(C)DT vs VCCDT vs TEMP Fig. 5 (IRS2153D) Fig. 6 (IRS2153D)
17908070)(C)60e (Vrut50C16aCrep40VmeT302010150-2502550751001252070120Frequency(kHz)Temperature (°C)VCC CLAMP vs TEMPTj vs. Frequency (SOIC)Fig. 7 Fig. 8
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IRS2153(1)D
300300250IsinkHO250IsinkLO))AAm200m200(( ttnnerr150uIsourceHOerr150uIsourceLOCCO H100OL100505000-250255075100125-250255075100125Temperature(C)Temperature(C)IsourceHO,IsinkHO vs Temp IsourceLO,IsinkLO vs Temp Fig. 9
Fig. 10
8070VOH_HO vs. Frequency)IB_CAPWith External BS diodeNo external BS diodemA60( 0V50161_S4014IB, AP3012C)_V( 10IB20IBS_10VOH10_8HO0V6-2502550751001254Temperature(C)20050100150200250300350400IBCAP, IBS10V vs TEMPFrequency (kHz) T=25°C, VS=0V, CHO = 1nF VOH_HO vs. Frequency vs. TempVCC=14V, CHO=1nF, VS=0V1412)10(V8_HO6VOH420hz046K2K50K75K00K1.125K1150K200KFrequency (kHz)T=-25cT=25cT=75cT=125cFig. 13 Fig. 11 Fig. 12 11
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IRS2153(1)D
IRS2153(1)DPbF
IRS2153(1)DSPbF
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IRS2153(1)D
LOADED TAPE FEED DIRECTIONB AH DF C NOTE : CONTROLLING DIMENSION IN MME G CARRIER TAPE DIMENSION FOR 8SOICNMetricImperialCodeMinMaxMinMaxA7.908.100.3110.318B 3.904.100.1530.161C11.7012.300.460.484D5.455.550.2140.218E6.306.500.2480.255F5.105.300.2000.208G1.50n/a0.059n/aH1.501.600.0590.062 F DCB E A G H REEL DIMENSIONS FOR 8SOICNMetricImperialCodeMinMaxMinMaxA329.60330.2512.97613.001B20.9521.450.8240.844C12.8013.200.5030.519D1.952.450.7670.096E98.00102.003.8584.015Fn/a18.40n/a0.724G14.5017.100.5700.673H12.4014.400.4880.566
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IRS2153(1)D
PART MARKING INFORMATION
ORDER INFORMATION
8-Lead PDIP IRS2153DPbF 8-Lead PDIP IRS21531DPbF 8-Lead SOIC IRS2153DSPbF 8-Lead SOIC IRS21531DSPbF 8-Lead SOIC Tape & Reel IRS2153DSTRPbF 8-Lead SOIC Tape & Reel IRS21531DSTRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/27/2006 14 因篇幅问题不能全部显示，请点此查看更多更全内容